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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
125 lines
3.8 KiB
C++
125 lines
3.8 KiB
C++
//===- GCNIterativeScheduler.h - GCN Scheduler ------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
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#define LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
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#include "GCNRegPressure.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/Support/Allocator.h"
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#include <limits>
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#include <memory>
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#include <vector>
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namespace llvm {
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class MachineInstr;
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class SUnit;
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class raw_ostream;
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class GCNIterativeScheduler : public ScheduleDAGMILive {
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using BaseClass = ScheduleDAGMILive;
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public:
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enum StrategyKind {
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SCHEDULE_MINREGONLY,
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SCHEDULE_MINREGFORCED,
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SCHEDULE_LEGACYMAXOCCUPANCY,
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SCHEDULE_ILP
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};
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GCNIterativeScheduler(MachineSchedContext *C,
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StrategyKind S);
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void schedule() override;
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void enterRegion(MachineBasicBlock *BB,
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned RegionInstrs) override;
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void finalizeSchedule() override;
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protected:
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using ScheduleRef = ArrayRef<const SUnit *>;
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struct TentativeSchedule {
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std::vector<MachineInstr *> Schedule;
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GCNRegPressure MaxPressure;
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};
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struct Region {
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// Fields except for BestSchedule are supposed to reflect current IR state
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// `const` fields are to emphasize they shouldn't change for any schedule.
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MachineBasicBlock::iterator Begin;
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// End is either a boundary instruction or end of basic block
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const MachineBasicBlock::iterator End;
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const unsigned NumRegionInstrs;
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GCNRegPressure MaxPressure;
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// best schedule for the region so far (not scheduled yet)
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std::unique_ptr<TentativeSchedule> BestSchedule;
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};
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SpecificBumpPtrAllocator<Region> Alloc;
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std::vector<Region*> Regions;
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MachineSchedContext *Context;
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const StrategyKind Strategy;
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mutable GCNUpwardRPTracker UPTracker;
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class BuildDAG;
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class OverrideLegacyStrategy;
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template <typename Range>
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GCNRegPressure getSchedulePressure(const Region &R,
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Range &&Schedule) const;
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GCNRegPressure getRegionPressure(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End) const;
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GCNRegPressure getRegionPressure(const Region &R) const {
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return getRegionPressure(R.Begin, R.End);
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}
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void setBestSchedule(Region &R,
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ScheduleRef Schedule,
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const GCNRegPressure &MaxRP = GCNRegPressure());
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void scheduleBest(Region &R);
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std::vector<MachineInstr*> detachSchedule(ScheduleRef Schedule) const;
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void sortRegionsByPressure(unsigned TargetOcc);
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template <typename Range>
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void scheduleRegion(Region &R, Range &&Schedule,
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const GCNRegPressure &MaxRP = GCNRegPressure());
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unsigned tryMaximizeOccupancy(unsigned TargetOcc =
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std::numeric_limits<unsigned>::max());
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void scheduleLegacyMaxOccupancy(bool TryMaximizeOccupancy = true);
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void scheduleMinReg(bool force = false);
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void scheduleILP(bool TryMaximizeOccupancy = true);
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void printRegions(raw_ostream &OS) const;
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void printSchedResult(raw_ostream &OS,
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const Region *R,
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const GCNRegPressure &RP) const;
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void printSchedRP(raw_ostream &OS,
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const GCNRegPressure &Before,
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const GCNRegPressure &After) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
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