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1192d7b254
The pattern is also mishandled by the generated matcher, so workaround this as in the DAG path. The existing DAG tests aren't particularly targeted to just this one intrinsic. These also end up differing in scheduling from SGPR->VGPR operand constraint copies.
223 lines
7.9 KiB
C++
223 lines
7.9 KiB
C++
//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#include "AMDGPU.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/IR/InstrTypes.h"
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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#undef AMDGPUSubtarget
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}
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namespace llvm {
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class AMDGPUInstrInfo;
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class AMDGPURegisterBankInfo;
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class GCNSubtarget;
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class MachineInstr;
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class MachineIRBuilder;
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class MachineOperand;
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class MachineRegisterInfo;
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class RegisterBank;
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class SIInstrInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class AMDGPUInstructionSelector : public InstructionSelector {
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private:
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MachineRegisterInfo *MRI;
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public:
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AMDGPUInstructionSelector(const GCNSubtarget &STI,
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const AMDGPURegisterBankInfo &RBI,
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const AMDGPUTargetMachine &TM);
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bool select(MachineInstr &I) override;
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static const char *getName();
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void setupMF(MachineFunction &MF, GISelKnownBits &KB,
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CodeGenCoverage &CoverageInfo) override;
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private:
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struct GEPInfo {
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const MachineInstr &GEP;
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SmallVector<unsigned, 2> SgprParts;
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SmallVector<unsigned, 2> VgprParts;
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int64_t Imm;
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GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
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};
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bool isInstrUniform(const MachineInstr &MI) const;
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bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
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const RegisterBank *getArtifactRegBank(
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Register Reg, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const;
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/// tblgen-erated 'select' implementation.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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MachineOperand getSubOperand64(MachineOperand &MO,
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const TargetRegisterClass &SubRC,
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unsigned SubIdx) const;
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bool selectCOPY(MachineInstr &I) const;
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bool selectPHI(MachineInstr &I) const;
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bool selectG_TRUNC(MachineInstr &I) const;
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bool selectG_SZA_EXT(MachineInstr &I) const;
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bool selectG_CONSTANT(MachineInstr &I) const;
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bool selectG_AND_OR_XOR(MachineInstr &I) const;
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bool selectG_ADD_SUB(MachineInstr &I) const;
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bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
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bool selectG_EXTRACT(MachineInstr &I) const;
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bool selectG_MERGE_VALUES(MachineInstr &I) const;
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bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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bool selectG_PTR_ADD(MachineInstr &I) const;
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bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
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bool selectG_INSERT(MachineInstr &I) const;
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bool selectInterpP1F16(MachineInstr &MI) const;
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bool selectG_INTRINSIC(MachineInstr &I) const;
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std::tuple<Register, unsigned, unsigned>
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splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
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bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
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bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
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bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
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int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
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bool selectG_ICMP(MachineInstr &I) const;
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bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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void initM0(MachineInstr &I) const;
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bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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bool selectG_FRAME_INDEX(MachineInstr &I) const;
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bool selectG_PTR_MASK(MachineInstr &I) const;
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bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
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bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
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std::pair<Register, unsigned>
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selectVOP3ModsImpl(Register Src) const;
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InstructionSelector::ComplexRendererFns
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selectVCSRC(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVSRC0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods_nnan(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OpSelMods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OpSelMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdImm(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdImm32(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectSmrdSgpr(MachineOperand &Root) const;
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template <bool Signed>
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InstructionSelector::ComplexRendererFns
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selectFlatOffsetImpl(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectFlatOffset(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectFlatOffsetSigned(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFScratchOffen(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectMUBUFScratchOffset(MachineOperand &Root) const;
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bool isDSOffsetLegal(Register Base, int64_t Offset,
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unsigned OffsetBits) const;
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std::pair<Register, unsigned>
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selectDS1Addr1OffsetImpl(MachineOperand &Src) const;
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InstructionSelector::ComplexRendererFns
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selectDS1Addr1Offset(MachineOperand &Root) const;
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void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx = -1) const;
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void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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bool isInlineImmediate16(int64_t Imm) const;
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bool isInlineImmediate32(int64_t Imm) const;
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bool isInlineImmediate64(int64_t Imm) const;
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bool isInlineImmediate(const APFloat &Imm) const;
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const SIInstrInfo &TII;
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const SIRegisterInfo &TRI;
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const AMDGPURegisterBankInfo &RBI;
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const AMDGPUTargetMachine &TM;
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const GCNSubtarget &STI;
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bool EnableLateStructurizeCFG;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#undef AMDGPUSubtarget
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // End llvm namespace.
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#endif
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