teak-llvm/llvm/lib/Target/AArch64
Guillaume Chatelet 805c157e8a [Alignment][NFC] Deprecate Align::None()
Summary:
This is a follow up on https://reviews.llvm.org/D71473#inline-647262.
There's a caveat here that `Align(1)` relies on the compiler understanding of `Log2_64` implementation to produce good code. One could use `Align()` as a replacement but I believe it is less clear that the alignment is one in that case.

Reviewers: xbolva00, courbet, bollu

Subscribers: arsenm, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, Jim, kerbowa, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73099
2020-01-24 12:53:58 +01:00
..
AsmParser [AArch64] Make AArch64 specific assembly directives case insensitive 2020-01-17 16:16:18 +00:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64.h
AArch64.td AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp Add function attribute "patchable-function-prefix" to support -fpatchable-function-entry=N,M where M>0 2020-01-23 17:02:27 -08:00
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
AArch64CallingConvention.h Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
AArch64CallingConvention.td [AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types 2019-12-12 09:49:22 +00:00
AArch64CallLowering.cpp [CodeGen] Make use of MachineInstrBuilder::getReg 2020-01-23 13:38:13 +00:00
AArch64CallLowering.h
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td [AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS 2020-01-16 15:18:44 -08:00
AArch64CompressJumpTables.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
AArch64ConditionOptimizer.cpp Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64FalkorHWPFFix.cpp [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
AArch64FastISel.cpp [AArch64] [Windows] Use COFF stubs for calls to extern_weak functions 2019-12-23 12:13:49 +02:00
AArch64FrameLowering.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64FrameLowering.h Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td DAG: Use TargetConstant for FENCE operands 2020-01-02 17:16:10 -05:00
AArch64InstrFormats.td [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64InstrInfo.cpp [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64InstrInfo.h [MachineScheduler] Allow clustering mem ops with complex addresses 2020-01-22 14:28:24 +00:00
AArch64InstrInfo.td [AArch64][SVE] Add first-faulting load intrinsic 2020-01-23 11:57:16 +00:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] Remove duplicate attribute lookup code that was supposed to be cached. NFC. 2020-01-23 15:50:08 -08:00
AArch64ISelDAGToDAG.cpp [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64ISelLowering.cpp [AArch64][SVE] Add first-faulting load intrinsic 2020-01-23 11:57:16 +00:00
AArch64ISelLowering.h [AArch64][SVE] Add first-faulting load intrinsic 2020-01-23 11:57:16 +00:00
AArch64LegalizerInfo.cpp [GlobalISel] Pass MachineOperands into MachineIRBuilder helper methods 2020-01-16 16:04:21 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp [AArch64] Don't rename registers with pseudo defs in Ld/St opt. 2020-01-22 09:26:25 -08:00
AArch64MachineFunctionInfo.h Revert "AArch64: Fix frame record chain" 2019-12-14 13:58:40 -08:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PreLegalizerCombiner.cpp [AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS 2020-01-16 15:18:44 -08:00
AArch64PromoteConstant.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
AArch64RedundantCopyElimination.cpp
AArch64RegisterBankInfo.cpp GlobalISel: Add type argument to getRegBankFromRegClass 2020-01-03 16:25:10 -05:00
AArch64RegisterBankInfo.h GlobalISel: Add type argument to getRegBankFromRegClass 2020-01-03 16:25:10 -05:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64RegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
AArch64RegisterInfo.td [NFC] Fix trivial typos in comments 2020-01-06 10:50:26 +00:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM3.td [AArch64] Update for Exynos 2019-11-12 14:37:41 -06:00
AArch64SchedExynosM4.td [AArch64] Update for Exynos 2019-11-12 14:37:41 -06:00
AArch64SchedExynosM5.td [AArch64] Add the pipeline model for Exynos M5 2019-11-22 15:09:17 -06:00
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td [AArch64] Add new scheduling predicates 2019-11-11 15:02:51 -06:00
AArch64SchedPredicates.td [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp 2019-11-23 19:11:31 +01:00
AArch64SchedThunderX2T99.td [AArch64] Remove overlapping scheduling definitions (NFC) 2019-10-30 13:57:27 -05:00
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64SpeculationHardening.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
AArch64StackOffset.h [SVE][CodeGen] Scalable vector MVT size queries 2019-11-18 12:30:59 +00:00
AArch64StackTagging.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
AArch64StackTaggingPreRA.cpp MTE: add more unchecked instructions. 2019-11-19 11:19:53 -08:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64Subtarget.h AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Add intrinsics for FFR manipulation 2020-01-24 10:58:12 +00:00
AArch64SystemOperands.td AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64TargetMachine.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp Revert "Honor -fuse-init-array when os is not specified on x86" 2019-12-17 07:36:59 -08:00
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
AArch64TargetTransformInfo.h [AArch64TTI] AArch64 supports NT vector stores through STNP. 2020-01-22 16:45:24 -08:00
CMakeLists.txt [gicombiner] Fix windows issue where single quotes in the command are passed through to tablegen 2019-10-02 23:38:06 +00:00
LLVMBuild.txt Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
SVEInstrFormats.td [AArch64][SVE] Add intrinsics for FFR manipulation 2020-01-24 10:58:12 +00:00