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89fbd55145
Adding __attribute__((aligned(32))) to __m256 breaks the implementation of _mm256_loadu_ps on Windows. On Windows, alignment attributes have higher precedence than packing attributes. We also might want to carefully consider the consequences of changing our vector typedefs, since many users copy them and invent their own new, non-Intel specific vector type names. llvm-svn: 333958
58 lines
2.8 KiB
C++
58 lines
2.8 KiB
C++
// RUN: %clang_cc1 -x c++ %s -O0 -triple=x86_64-apple-darwin -target-feature +avx2 -fmax-type-align=16 -emit-llvm -o - -Werror | FileCheck %s
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// rdar://16254558
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typedef float AVX2Float __attribute__((__vector_size__(32)));
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volatile float TestAlign(void)
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{
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volatile AVX2Float *p = new AVX2Float;
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*p = *p;
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AVX2Float r = *p;
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return r[0];
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}
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// CHECK: [[R:%.*]] = alloca <8 x float>, align 32
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// CHECK-NEXT: [[CALL:%.*]] = call i8* @_Znwm(i64 32)
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// CHECK-NEXT: [[ZERO:%.*]] = bitcast i8* [[CALL]] to <8 x float>*
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// CHECK-NEXT: store <8 x float>* [[ZERO]], <8 x float>** [[P:%.*]], align 8
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// CHECK-NEXT: [[ONE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: [[TWO:%.*]] = load volatile <8 x float>, <8 x float>* [[ONE]], align 16
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// CHECK-NEXT: [[THREE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: store volatile <8 x float> [[TWO]], <8 x float>* [[THREE]], align 16
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// CHECK-NEXT: [[FOUR:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: [[FIVE:%.*]] = load volatile <8 x float>, <8 x float>* [[FOUR]], align 16
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// CHECK-NEXT: store <8 x float> [[FIVE]], <8 x float>* [[R]], align 32
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// CHECK-NEXT: [[SIX:%.*]] = load <8 x float>, <8 x float>* [[R]], align 32
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x float> [[SIX]], i32 0
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// CHECK-NEXT: ret float [[VECEXT]]
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typedef float AVX2Float_Explicitly_aligned __attribute__((__vector_size__(32))) __attribute__((aligned (32)));
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typedef AVX2Float_Explicitly_aligned AVX2Float_indirect;
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typedef AVX2Float_indirect AVX2Float_use_existing_align;
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volatile float TestAlign2(void)
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{
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volatile AVX2Float_use_existing_align *p = new AVX2Float_use_existing_align;
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*p = *p;
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AVX2Float_use_existing_align r = *p;
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return r[0];
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}
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// CHECK: [[R:%.*]] = alloca <8 x float>, align 32
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// CHECK-NEXT: [[CALL:%.*]] = call i8* @_Znwm(i64 32)
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// CHECK-NEXT: [[ZERO:%.*]] = bitcast i8* [[CALL]] to <8 x float>*
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// CHECK-NEXT: store <8 x float>* [[ZERO]], <8 x float>** [[P:%.*]], align 8
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// CHECK-NEXT: [[ONE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: [[TWO:%.*]] = load volatile <8 x float>, <8 x float>* [[ONE]], align 32
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// CHECK-NEXT: [[THREE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: store volatile <8 x float> [[TWO]], <8 x float>* [[THREE]], align 32
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// CHECK-NEXT: [[FOUR:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8
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// CHECK-NEXT: [[FIVE:%.*]] = load volatile <8 x float>, <8 x float>* [[FOUR]], align 32
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// CHECK-NEXT: store <8 x float> [[FIVE]], <8 x float>* [[R]], align 32
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// CHECK-NEXT: [[SIX:%.*]] = load <8 x float>, <8 x float>* [[R]], align 32
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// CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x float> [[SIX]], i32 0
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// CHECK-NEXT: ret float [[VECEXT]]
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