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7339e61b89
Use the new cx8 feature flag that was added to the backend to represent support for cmpxchg8b. Use this flag to set the MaxAtomicInlineWidth. This also assumes all the cmpxchg instructions are enabled for CK_Generic which is what cc1 defaults to when nothing is specified. Differential Revision: https://reviews.llvm.org/D59566 llvm-svn: 356709
23 lines
577 B
C
23 lines
577 B
C
// RUN: %clang_cc1 -triple i386-linux-gnu -emit-llvm %s -o - | FileCheck %s
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// Picking a cpu that doesn't have mmx or sse by default so we can enable it later.
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#define __MM_MALLOC_H
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#include <x86intrin.h>
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// Verify that when we turn on sse that we also turn on mmx.
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void __attribute__((target("sse"))) shift(__m64 a, __m64 b, int c) {
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_mm_slli_pi16(a, c);
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_mm_slli_pi32(a, c);
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_mm_slli_si64(a, c);
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_mm_srli_pi16(a, c);
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_mm_srli_pi32(a, c);
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_mm_srli_si64(a, c);
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_mm_srai_pi16(a, c);
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_mm_srai_pi32(a, c);
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}
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// CHECK: "target-features"="+cx8,+mmx,+sse,+x87"
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