teak-llvm/clang/test/CodeGen/aarch64-sve-inline-asm.c
Sander de Smalen 2b290885d9 [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list
Adds the SVE vector and predicate registers to the list of known registers.

Patch by Kerry McLaughlin.

Reviewers: erichkeane, sdesmalen, rengolin

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D64739

llvm-svn: 366878
2019-07-24 08:42:34 +00:00

14 lines
356 B
C

// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
void test_sve_asm() {
asm volatile(
"ptrue p0.d\n"
"ptrue p15.d\n"
"add z0.d, p0/m, z0.d, z0.d\n"
"add z31.d, p0/m, z31.d, z31.d\n"
:
:
: "z0", "z31", "p0", "p15");
// CHECK: "~{z0},~{z31},~{p0},~{p15}"
}