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ed96b58bd2
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91 Commits

Author SHA1 Message Date
Owen Anderson
ed96b58bd2 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson
03aadae01f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
James Molloy
db4ce60328 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson
4af0aa98d5 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
Owen Anderson
2fa06a7226 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson
b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson
240d20af79 Spelling fail. 
llvm-svn: 138667
 2011-08-26 21:47:57 +00:00
Owen Anderson
16d33f36d5 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Owen Anderson
5658b49f64 Update for feedback from Jim. 
llvm-svn: 138642
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
aa38dbadca ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

llvm-svn: 138636
 2011-08-26 18:21:36 +00:00
Owen Anderson
a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Owen Anderson
149695627a Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625
 2011-08-26 06:19:51 +00:00
Owen Anderson
5e30972cff Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
llvm-svn: 138575
 2011-08-25 18:30:18 +00:00
Owen Anderson
37612a3de3 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
llvm-svn: 138507
 2011-08-24 22:40:22 +00:00
Owen Anderson
216cfaa808 Be careful not to walk off the end of the operand info list while updating VFP predicates. 
llvm-svn: 138492
 2011-08-24 21:35:46 +00:00
Evan Cheng
2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Owen Anderson
523004145e Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
llvm-svn: 138443
 2011-08-24 17:21:43 +00:00
Owen Anderson
924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Owen Anderson
9b7bd15d0b Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
llvm-svn: 138339
 2011-08-23 17:45:18 +00:00
Owen Anderson
eb1367b2b8 Reject invalid imod values in t2CPS instructions. 
llvm-svn: 138306
 2011-08-22 23:44:04 +00:00
Owen Anderson
df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00
Owen Anderson
721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Owen Anderson
ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Owen Anderson
b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Owen Anderson
96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson
192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson
5d2db89ba6 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
llvm-svn: 137997
 2011-08-18 22:15:25 +00:00
Owen Anderson
67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Jim Grosbach
d14b70d00b Tidy up. 80 columns. 
llvm-svn: 137881
 2011-08-17 21:58:18 +00:00
Jim Grosbach
46dd413991 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
 2011-08-17 21:51:27 +00:00
Owen Anderson
187e1e46f9 Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. 
llvm-svn: 137838
 2011-08-17 18:14:48 +00:00
Owen Anderson
a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Owen Anderson
91a8f9be20 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
llvm-svn: 137787
 2011-08-16 23:45:44 +00:00
Owen Anderson
a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Owen Anderson
1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson
b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson
2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson
60138eaf93 Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson
3987a61c16 Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Owen Anderson
c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Jim Grosbach
e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson
ff0b442330 Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson
2f7aa73312 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Owen Anderson
b685c9f011 Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Owen Anderson
3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson
6066340301 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Owen Anderson
3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Owen Anderson
0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson
ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00