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3 Commits

Author SHA1 Message Date
Alex Bradbury
9330e64485 [RISCV] Add basic support for inline asm constraints 
llvm-svn: 322217
 2018-01-10 20:05:09 +00:00
Alex Bradbury
ec8aa91305 [RISCV] Codegen support for memory operations on global addresses 
Differential Revision: https://reviews.llvm.org/D39103

llvm-svn: 317688
 2017-11-08 13:24:21 +00:00
Alex Bradbury
8971842f43 [RISCV] Initial codegen support for ALU operations 
This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933

llvm-svn: 316188
 2017-10-19 21:37:38 +00:00