Gericom/teak-llvm
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2 Commits

Author SHA1 Message Date
Jim Grosbach
667b147dba ARM: Constrain regclass for TSTri instruction. 
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274
 2013-08-26 20:22:05 +00:00
Chad Rosier
6d68c7cf79 [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too. 
llvm-svn: 149730
 2012-02-04 00:39:19 +00:00