Commit Graph

19 Commits

Author SHA1 Message Date
Tim Northover
23b1f08282 ARM64: optimise (cmp x, (sub 0, y)) to (cmn x, y).
This transformation is only valid when being used for an EQ or NE
comparison since the flags change otherwise.

llvm-svn: 206167
2014-04-14 12:50:47 +00:00
Jim Grosbach
d3249d0923 [ARM64,C++11]: More range-based loop simplification.
llvm-svn: 206006
2014-04-11 00:27:19 +00:00
Tim Northover
b36d428d27 ARM64: scalarize v1i64 mul operation
This is the second part of fixing PR19367.

llvm-svn: 205836
2014-04-09 07:07:02 +00:00
Tim Northover
07a8ff4892 ARM64: handle v1i1 types arising from setcc properly.
There were several overlapping problems here, and this solution is
closely inspired by the one adopted in AArch64 in r201381.

Firstly, scalarisation of v1i1 setcc operations simply fails if the
input types are legal. This is fixed in LegalizeVectorTypes.cpp this
time, and allows AArch64 code to be simplified slightly.

Second, vselect with such a setcc feeding into it ends up in
ScalarizeVectorOperand, where it's not handled. I experimented with an
implementation, but found that whatever DAG came out was rather
horrific. I think Hao's DAG combine approach is a good one for
quality, though there are edge cases it won't catch (to be fixed
separately).

Should fix PR19335.

llvm-svn: 205625
2014-04-04 14:49:21 +00:00
Tim Northover
85d6a16c46 ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts
The previous patterns directly inserted FMOV or INS instructions into
the DAG for scalar_to_vector & bitconvert patterns. This is horribly
inefficient and can generated lots more GPR <-> FPR register traffic
than necessary.

It's much better to emit instructions the register allocator
understands so it can coalesce the copies when appropriate.

It led to at least one ISelLowering hack to avoid the problems, which
was incorrect for v1i64 (FPR64 has no dsub). It can now be removed
entirely.

This should also fix PR19331.

llvm-svn: 205616
2014-04-04 09:03:09 +00:00
Craig Topper
840beec2d0 Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
llvm-svn: 205610
2014-04-04 05:16:06 +00:00
Tim Northover
2ad88d3aab ARM64: always use i64 for the RHS of shift operations
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.

Should fix PR19294.

llvm-svn: 205519
2014-04-03 09:26:16 +00:00
Tim Northover
c7c6a93704 ARM64: don't generate __sincos_stret calls unless on MachO
This should fix PR19314.

llvm-svn: 205514
2014-04-03 07:06:13 +00:00
Jim Grosbach
2a2459f365 Make a few more range-based loops use explicit types.
No functional change.

llvm-svn: 205458
2014-04-02 20:21:22 +00:00
Jim Grosbach
020e657790 [C++11,ARM64] Range based for loops in target lowering.
No functional change intended.

llvm-svn: 205443
2014-04-02 18:00:51 +00:00
Tim Northover
0d80f70530 ARM64: fix lowering of fp128 fptosi/fptoui
We were creating libcall nodes that returned an MVT::f128, when these
particular operations actually return an int of some stripe.

llvm-svn: 205425
2014-04-02 14:39:07 +00:00
Tim Northover
ebd37ab382 ARM64: make sure first argument to INSERT_SUBVECTOR has right type.
Again, coalescing and other optimisations swiftly made the MachineInstrs
consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was
produced.

llvm-svn: 205423
2014-04-02 14:38:58 +00:00
Aaron Ballman
d1726ee8fa Fixing warnings in the MSVC build. No functional changes intended.
llvm-svn: 205301
2014-04-01 12:22:20 +00:00
Chandler Carruth
d28515af31 [ARM64] Fix materialization of an fp128 zero immediate. There currently
is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.

llvm-svn: 205161
2014-03-31 00:02:10 +00:00
Tim Northover
6b3258f087 ARM64: remove unused variables
llvm-svn: 205133
2014-03-30 07:35:48 +00:00
Dmitri Gribenko
1fd72104ad Fix a few -Wdocumentation warnings
llvm-svn: 205116
2014-03-29 19:40:32 +00:00
Benjamin Kramer
61e595be4d ARM64: Remove unused helper function, make others static.
llvm-svn: 205112
2014-03-29 18:00:49 +00:00
Tim Northover
2125374ecf ARM64: use 64-bit constant even on 32-bit machines
Another existing bot failure so no tests.

llvm-svn: 205093
2014-03-29 11:51:49 +00:00
Tim Northover
00ed9964c6 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
2014-03-29 10:18:08 +00:00