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Author SHA1 Message Date
David Woodhouse
caaa2850c0 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

llvm-svn: 199654
 2014-01-20 12:02:53 +00:00
Craig Topper
35da3d190a Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
llvm-svn: 199364
 2014-01-16 07:36:58 +00:00
Craig Topper
b7c7f38918 Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
llvm-svn: 199295
 2014-01-15 05:02:02 +00:00
Craig Topper
ad60708a72 Remove stray comma in enum to satisfy -Wpedantic. 
llvm-svn: 199194
 2014-01-14 08:07:10 +00:00
Craig Topper
ae11aed9d7 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
David Woodhouse
32da3c8f3b [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
 2014-01-08 12:58:24 +00:00
Craig Topper
2ea87dad77 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
llvm-svn: 198589
 2014-01-06 06:57:27 +00:00
Craig Topper
d9e1669d1c Use patterns to remove some duplicate instructions. 
llvm-svn: 198550
 2014-01-05 06:55:48 +00:00
Craig Topper
34db6523f3 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
llvm-svn: 198547
 2014-01-05 05:46:38 +00:00
Craig Topper
c0107977d9 Remove no longer needed x86 disassembler hack. 
llvm-svn: 198546
 2014-01-05 05:10:07 +00:00
Craig Topper
0550ce7ac1 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper
5165cf78b0 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
llvm-svn: 198544
 2014-01-05 04:32:42 +00:00
Craig Topper
3484fc2161 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper
5999d47538 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
llvm-svn: 198530
 2014-01-05 01:35:51 +00:00
Craig Topper
bc281ad8c1 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
llvm-svn: 198515
 2014-01-04 22:29:41 +00:00
Craig Topper
1da8582322 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
llvm-svn: 198475
 2014-01-04 05:09:27 +00:00
Craig Topper
66c20f344e Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
llvm-svn: 198336
 2014-01-02 19:12:10 +00:00
Craig Topper
fae226c67e Remove unused HasFROperands field from disassembler. 
llvm-svn: 198332
 2014-01-02 18:44:21 +00:00
Craig Topper
eabdbcb8a9 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Craig Topper
a941d2b08e Remove unnecessary stirng comparison from disassembler. 
llvm-svn: 198325
 2014-01-02 17:41:40 +00:00
Craig Topper
9dd48c8ed4 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Craig Topper
83b7e24b76 Remove unused function argument. 
llvm-svn: 198291
 2014-01-02 03:58:45 +00:00
Craig Topper
3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Craig Topper
9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Craig Topper
623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper
e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper
0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00
Craig Topper
6d776e2660 Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. 
llvm-svn: 198226
 2013-12-30 17:37:10 +00:00
Eric Christopher
c0a5aaeab0 [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768
 2013-12-20 02:04:49 +00:00
Elena Demikhovsky
47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Craig Topper
a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
llvm-svn: 192567
 2013-10-14 04:55:01 +00:00
Craig Topper
88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Craig Topper
aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
llvm-svn: 192522
 2013-10-12 04:46:18 +00:00
Craig Topper
81034928c6 Remove another unnecessary filter from the disassembler. 
llvm-svn: 192425
 2013-10-11 06:59:57 +00:00
Craig Topper
e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
llvm-svn: 192339
 2013-10-10 04:26:52 +00:00
Craig Topper
2d0d180ab4 More x86 disassembler filtering cleanup. 
llvm-svn: 192279
 2013-10-09 06:12:53 +00:00
Craig Topper
043d749ba3 Remove some old filters from the x86 disassembler table builder. 
llvm-svn: 192275
 2013-10-09 05:02:29 +00:00
Craig Topper
a984729f8a Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
llvm-svn: 192175
 2013-10-08 06:30:39 +00:00
Craig Topper
72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
llvm-svn: 192171
 2013-10-08 05:53:50 +00:00
Craig Topper
07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
llvm-svn: 192090
 2013-10-07 07:19:47 +00:00
Craig Topper
2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
llvm-svn: 192086
 2013-10-07 04:28:06 +00:00
Craig Topper
9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Elena Demikhovsky
c35219e3ee AVX-512: Added masked SHIFT commands, more encoding tests 
llvm-svn: 189005
 2013-08-22 12:18:28 +00:00
Craig Topper
9469e906a5 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. 
llvm-svn: 187333
 2013-07-28 21:28:02 +00:00
Elena Demikhovsky
baf51e3e61 fixed compilation issue 
llvm-svn: 187325
 2013-07-28 08:45:12 +00:00
Elena Demikhovsky
003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Stefanus Du Toit
8811ad4f81 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
 2013-06-18 17:08:10 +00:00
Michael Liao
95d9440348 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.

llvm-svn: 179266
 2013-04-11 04:52:28 +00:00
Dave Zarzycki
656e8515fc x86 -- add the XTEST instruction 
llvm-svn: 177888
 2013-03-25 18:59:43 +00:00
Kevin Enderby
f15856ebb4 Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048

llvm-svn: 176828
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo
ab588efe42 Added 0x0D to 2-byte opcode extension table for prefetch* variants 
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920
 2013-02-12 00:19:12 +00:00
Chandler Carruth
91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Michael Liao
73cffddb95 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
 2012-11-08 07:28:54 +00:00
Craig Topper
3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper
c30fdbc46c Add support for converting llvm.fma to fma4 instructions. 
llvm-svn: 162999
 2012-08-31 15:40:30 +00:00
Craig Topper
c6b7ef61f4 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
llvm-svn: 160951
 2012-07-30 06:48:11 +00:00
Craig Topper
08ead0b14e Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly 
llvm-svn: 160950
 2012-07-30 06:27:19 +00:00
Craig Topper
6f4ad80dc8 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. 
llvm-svn: 160949
 2012-07-30 05:39:34 +00:00
Craig Topper
b58dc17025 Simplify code that filtered certain instructions in two different ways. No functional change. 
llvm-svn: 160948
 2012-07-30 05:10:05 +00:00
Craig Topper
60a58ac3e2 Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway. 
llvm-svn: 160946
 2012-07-30 04:53:00 +00:00
Craig Topper
ac172e225d Remove trailing whitespace. 
llvm-svn: 160945
 2012-07-30 04:48:12 +00:00
Craig Topper
c7690ac7ac Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. 
llvm-svn: 160775
 2012-07-26 07:48:28 +00:00
Richard Trieu
9208abd7c3 Move around some enum elements so that lastMRM corrects gets assigned 56, which 
is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.

llvm-svn: 160465
 2012-07-18 23:04:22 +00:00
Craig Topper
01deb5f2df Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00
Craig Topper
f7755df776 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
llvm-svn: 160110
 2012-07-12 06:52:41 +00:00
Manman Ren
a09820414a X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221
 2012-06-26 19:47:59 +00:00
Benjamin Kramer
ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper
7629d63bc4 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Kevin Enderby
014e1cde5f Fix the x86 disassembler to at least print the lock prefix if it is the first 
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414
 2012-03-09 17:52:49 +00:00
Craig Topper
6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Craig Topper
66a3597a4a Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Craig Topper
ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Craig Topper
2ba766ae84 Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper
03a0beda88 Add FMA4 instructions to disassembler. 
llvm-svn: 147367
 2011-12-30 05:20:36 +00:00
Craig Topper
75ffc5fbb5 Remove some unnecessary filtering checks from X86 disassembler table build. 
llvm-svn: 144986
 2011-11-19 05:48:20 +00:00
Craig Topper
f01f1b5cb9 More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Craig Topper
980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper
96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper
aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Craig Topper
25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper
27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Craig Topper
965de2c197 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper
a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Craig Topper
23eb468b1f Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
llvm-svn: 141274
 2011-10-06 06:44:41 +00:00
Craig Topper
f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Craig Topper
d07a59f288 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
88cb33e0d4 Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Craig Topper
526adabe87 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
llvm-svn: 140370
 2011-09-23 06:57:25 +00:00
Craig Topper
ee8157cb41 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
llvm-svn: 139691
 2011-09-14 06:41:26 +00:00
Craig Topper
e98d8a5c84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
llvm-svn: 139588
 2011-09-13 06:54:58 +00:00
Craig Topper
a88e356017 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. 
llvm-svn: 139485
 2011-09-11 21:41:45 +00:00
Craig Topper
a948cb9058 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. 
llvm-svn: 139484
 2011-09-11 20:23:20 +00:00
Kevin Enderby
54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Craig Topper
4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
llvm-svn: 138795
 2011-08-30 07:09:35 +00:00
Kevin Enderby
7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
David Greene
af8ee2cdee Unconstify Inits 
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
 2011-07-29 22:43:06 +00:00
David Greene
1aa0e3e118 [AVX] Constify Inits 
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
 2011-07-29 19:07:05 +00:00