Commit Graph

33992 Commits

Author SHA1 Message Date
Dan Gohman
0553299586 [WebAssembly] Re-enable loop idiom recognition for memcpy et al.
llvm-svn: 258125
2016-01-19 14:49:23 +00:00
Asaf Badouh
d4a0d9a78c [X86][AVX512]fix dag & add intrinsics for fixupimm
cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics

Differential Revision: http://reviews.llvm.org/D16313

llvm-svn: 258124
2016-01-19 14:21:39 +00:00
Tobias Edler von Koch
8ecaf69291 [LTO] Restore original linkage of externals prior to splitting
Summary:
This is a companion patch for http://reviews.llvm.org/D16124.

Internalized symbols increase the size of strongly-connected components in
SCC-based module splitting and thus reduce the amount of parallelism. This
patch records the original linkage of non-local symbols prior to
internalization and then restores it just before splitting/CodeGen. This is
also useful for cases where the linker requires symbols to remain external, for
instance, so they can be placed according to linker script rules.

It's currently under its own flag (-restore-globals) but should eventually
share a common flag with D16124.

Reviewers: joker.eph, pcc

Subscribers: slarin, llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D16229

llvm-svn: 258100
2016-01-18 23:24:54 +00:00
Matt Arsenault
33e3ecee0c AMDGPU: Reduce 64-bit SRAs
llvm-svn: 258096
2016-01-18 22:09:04 +00:00
Matt Arsenault
6e3a45193a AMDGPU: Split 64-bit and of constant up
This breaks the tests that were meant for testing
64-bit inline immediates, so move those to shl where
they won't be broken up.

This should be repeated for the other related bit ops.

llvm-svn: 258095
2016-01-18 22:01:13 +00:00
Simon Pilgrim
77d86d1c08 [X86][AVX2] Ensure integer execution domain for integer blend tests
llvm-svn: 258094
2016-01-18 21:58:21 +00:00
Matt Arsenault
3cbbc10488 AMDGPU: Generalize shl combine
Reduce 64-bit shl with constant > 32. We already special cased
this for the == 32 case, but this also works for any >= 32 constant.

llvm-svn: 258092
2016-01-18 21:55:14 +00:00
Simon Pilgrim
3ca2f21f50 [X86][SSE] Regenerate vector blend commutation tests
llvm-svn: 258091
2016-01-18 21:46:46 +00:00
Matt Arsenault
80edab99ff AMDGPU: Reduce 64-bit lshr by constant to 32-bit
64-bit shifts are very slow on some subtargets.

llvm-svn: 258090
2016-01-18 21:43:36 +00:00
Davide Italiano
5e82324fe4 [JIT] Add small-code model test for ELF.
The coverage is almost non-existent, hopefully more will come after this.

Differential Revision:	http://reviews.llvm.org/D16096

llvm-svn: 258087
2016-01-18 21:14:12 +00:00
Matt Arsenault
4085e8fcef AMDGPU: Cleanup sra test
llvm-svn: 258086
2016-01-18 21:13:56 +00:00
Sergei Larin
d19d4d30d8 Add to the split module utility an SCC based method which allows not to globalize any local variables.
Summary:
    Currently llvm::SplitModule as the first step globalizes all local objects, which might not be desirable in some scenarios.
    This change adds a new flag to llvm::SplitModule that uses SCC approach to search for a balanced partition without the need to externalize symbols.
    Such partition might not be possible or fully balanced for a given number of partitions, and is a function of the module properties (global/local dependencies within the module).
    
    Joint development Tobias Edler von Koch (tobias@codeaurora.org) and Sergei Larin (slarin@codeaurora.org)
    
    Subscribers: llvm-commits, joker.eph
    
    Differential Revision: http://reviews.llvm.org/D16124

llvm-svn: 258083
2016-01-18 21:07:13 +00:00
Simon Pilgrim
3e5fb61978 [X86][AVX2] Broadcast subvectors
AVX2 can only broadcast from the zero'th element of a vector, but if the broadcastable element is the zero'th element of a 128-bit subvector its advantageous to extract the subvector, broadcast from that and avoid the loading of shuffle mask data that would be needed for VPERMPS/VPERMD. The only exception being when the source type is 4f64 or 4i64 which can directly use the immediate shuffle VPERMPD/VPERMQ directly.

Differential Revision: http://reviews.llvm.org/D16050

llvm-svn: 258081
2016-01-18 20:59:04 +00:00
Igor Breger
239fda676c AVX512: Masked store intrinsic implementation.
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
2016-01-18 13:52:57 +00:00
Igor Breger
dd6522c653 AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl instruction.
code example , previous implementation.
    movzbl  %dil, %eax
    kmovw  %eax, %k0
  new code
    kmovw  %edi, %k0

Differential Revision: http://reviews.llvm.org/D16287

llvm-svn: 258045
2016-01-18 12:02:45 +00:00
Oliver Stannard
9f68749eba [ARM] Operands for PKHTB alias should be swapped
When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of
the input operands needs to be swapped.

Differential Revision: http://reviews.llvm.org/D16288

llvm-svn: 258044
2016-01-18 11:56:35 +00:00
Sanjoy Das
de47590589 [IndVars] Fix PR25576
`LCSSASafePhiForRAUW` as computed was incorrect -- in cases like
these (this exact example does not actually trigger the bug):

define i32 @f(i32 %n, i1* %c) {
entry:
  br label %outer.loop

outer.loop:
  br label %inner.loop

inner.loop:
  %iv = phi i32 [ 0, %outer.loop ], [ %iv.inc, %inner.loop ]
  %iv.inc = add nuw nsw i32 %iv, 1
  %tc = udiv i32 %n, 13
  %be.cond = icmp ult i32 %iv, %tc
  br i1 %be.cond, label %inner.loop, label %inner.exit

inner.exit:
  %iv.lcssa = phi i32 [ %iv, %inner.loop ]
  %outer.be.cond = load volatile i1, i1* %c
  br i1 %outer.be.cond, label %outer.loop, label %leave

leave:
  %iv.lcssa.lcssa = phi i32 [ %iv.lcssa, %inner.exit ]
  ret i32 %iv.lcssa.lcssa
}

`LCSSASafePhiForRAUW` is true for `%iv.lcssa` when re-rewriting the exit
value of `%iv` for `%inner.loop` to `%tc` (this can happen due to
`SCEVExpander::findExistingExpansion`), but the RAUW breaks LCSSA.

To fix this, instead of computing `SafePhi` with special logic, decide
the safety of RAUW directly via `replacementPreservesLCSSAForm`.

llvm-svn: 258016
2016-01-17 18:12:52 +00:00
Simon Pilgrim
6daac27d98 [X86][AVX512] Regenerate v1 shuffle tests
llvm-svn: 258013
2016-01-17 14:53:17 +00:00
Artur Pilipenko
f84dc06e5b Push isDereferenceableAndAlignedPointer down into isSafeToLoadUnconditionally
Reviewed By: reames

Differential Revision: http://reviews.llvm.org/D16226

llvm-svn: 258010
2016-01-17 12:35:29 +00:00
Michael Zuckerman
ac1b238b0a [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics
Differential Revision: http://reviews.llvm.org/D16189

llvm-svn: 258008
2016-01-17 11:33:29 +00:00
Michael Zuckerman
ede597c753 [AVX512] Adding VPERMQ VPERMPD Intrinsics
Differential Revision: http://reviews.llvm.org/D16194

llvm-svn: 258006
2016-01-17 08:32:14 +00:00
Lang Hames
4ce7cc0f4c Remove some stale comments and fix a typo as suggested by David Blaikie in his
review of r257343.

Thanks Dave!

llvm-svn: 258002
2016-01-17 01:49:46 +00:00
Simon Atanasyan
72155c33b1 [llvm-readobj][ELF] Teach llvm-readobj to show dynamic relocation in REL format
MIPS 32-bit ABI uses REL relocation record format to save dynamic
relocations. The patch teaches llvm-readobj to show dynamic relocations
in this format.

Differential Revision: http://reviews.llvm.org/D16114

llvm-svn: 258001
2016-01-16 22:40:09 +00:00
Simon Pilgrim
20f31fa31a [X86][AVX] Enable extraction of upper 128-bit subvectors for 'half undef' shuffle lowering
Added support for the extraction of the upper 128-bit subvectors for lower/upper half undef shuffles if it would reduce the number of extractions/insertions or avoid loads of AVX2 permps/permd shuffle masks.

Minor follow up to D15477.

llvm-svn: 258000
2016-01-16 22:30:20 +00:00
Simon Pilgrim
7cdedc1e02 [X86][SSE] Added extra 'float3' consecutive load tests
llvm-svn: 257998
2016-01-16 19:53:33 +00:00
Manman Ren
53a54c41d7 CXX_FAST_TLS calling convention: fix issue on x86-64.
%RBP can't be handled explicitly. We generate the following code:
    pushq %rbp
    movq  %rsp, %rbp
    ...
    movq  %rbx, (%rbp)  ## 8-byte Spill
where %rbp will be overwritten by the spilled value.

The fix is to let PEI handle %RBP.
PR26136

llvm-svn: 257997
2016-01-16 16:39:46 +00:00
Simon Pilgrim
8270fe5960 [X86][SSE] Regenerated SSE4 CRC32 and v2i64 comparison tests
llvm-svn: 257996
2016-01-16 15:41:42 +00:00
Simon Pilgrim
726622394f [X86][AVX] Regenerated AVX tests
Updated i1 select, vector truncation and subvector extraction tests

llvm-svn: 257995
2016-01-16 15:25:02 +00:00
Simon Pilgrim
48bec72db3 [X86]AVX] Tidyup shift/splat tests
Missing comments, fixed bad word wrapping

llvm-svn: 257993
2016-01-16 15:13:58 +00:00
Simon Pilgrim
ecd07946eb [X86][SSE] Regenerated HADD/HSUB tests
llvm-svn: 257992
2016-01-16 14:03:40 +00:00
Igor Laevsky
28eeb3f66c [BasicAliasAnalysis] Take into account operand bundles in the getModRefInfo function
Differential Revision: http://reviews.llvm.org/D16225

llvm-svn: 257991
2016-01-16 12:15:53 +00:00
George Rimar
e05fcecd36 Fixed CRLF->LF line endings from r257914. NFC.
llvm-svn: 257990
2016-01-16 10:38:32 +00:00
Davide Italiano
8c50367276 [llvm-readobj] Dump DT_RELACOUNT correctly.
llvm-svn: 257988
2016-01-16 06:06:36 +00:00
Xinliang David Li
6ed987dffe [PGO] fix a bug in profile summary computation
Entry block count was not counted and is corrected. Also
introduce a new metric that is MaxInternalBlockCount which
show command shows (as before).

llvm-svn: 257987
2016-01-16 05:29:49 +00:00
Keno Fischer
bc0cb11eb2 [DwarfDebug] Don't merge DebugLocEntries if their pieces overlap
Summary:
Later in DWARF emission we check that DebugLocEntries have
non-overlapping pieces, so we should create any such entries
by merging here.

Fixes PR26163.

Reviewers: aprantl
Differential Revision: http://reviews.llvm.org/D16249

llvm-svn: 257979
2016-01-16 01:15:32 +00:00
Peter Collingbourne
f0f5e87083 Introduce sanstats tool and llvm::CreateSanitizerStatReport function.
This is part of a new statistics gathering feature for the sanitizers.
See clang/docs/SanitizerStats.rst for further info and docs.

Differential Revision: http://reviews.llvm.org/D16174

llvm-svn: 257970
2016-01-16 00:31:11 +00:00
Dan Gohman
2f301f3e92 [WebAssembly] Don't create a needless .note.GNU-stack section
WebAssembly's stack will never be executable by default, so it isn't
necessary to declare .note.GNU-stack sections to request a non-executable
stack.

Differential Revision: http://reviews.llvm.org/D15969

llvm-svn: 257962
2016-01-15 23:59:13 +00:00
Artem Belevich
5be0706ebe [NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
llvm-svn: 257961
2016-01-15 23:57:53 +00:00
Dan Gohman
f2f92f1474 [WebAssembly] Re-enable a test.
Out-of-tree projects that don't support this can disable the test for
themselves rather than having it disabled in LLVM itself.

llvm-svn: 257960
2016-01-15 23:47:19 +00:00
Reid Kleckner
af49ecb286 [codeview] Handle multiple frame descriptions in readobj
llvm-svn: 257943
2016-01-15 22:09:13 +00:00
Dan Gohman
5d7ec435e3 Remove a now-empty file left behind by r257940.
llvm-svn: 257942
2016-01-15 22:07:35 +00:00
Dan Gohman
4e9b2a60ab [SelectionDAG] CSE nodes with differing SDNodeFlags
In the optimizer (GVN etc.) when eliminating redundant nodes with different
flags, the flags are ignored for the purposes of testing for congruence, and
then intersected for the purposes of producing a result that supports the union
of all the uses. This commit makes SelectionDAG's CSE do the same thing,
allowing it to CSE nodes in more cases. This fixes PR26063.

Differential Revision: http://reviews.llvm.org/D15957

llvm-svn: 257940
2016-01-15 21:56:40 +00:00
Manman Ren
e5f807f928 CXX_FAST_TLS calling convention: fix issue on ARM.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

PR26136

llvm-svn: 257930
2016-01-15 20:24:11 +00:00
Manman Ren
4632e8e625 CXX_FAST_TLS calling convention: fix issue on AArch64.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

I will commit fixes to other platforms as well.

PR26136

llvm-svn: 257929
2016-01-15 20:13:28 +00:00
Manman Ren
4fe01bd8f9 CXX_FAST_TLS calling convention: fix issue on X86-64.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

I will commit fixes to other platforms as well.

PR26136

llvm-svn: 257925
2016-01-15 19:35:42 +00:00
Reid Kleckner
d4a0d18899 Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline"
This reverts commit r257883.

Somehow this didn't make it into r257916.

llvm-svn: 257919
2016-01-15 18:55:12 +00:00
Matthew Simpson
57fe1b10db Reapply r257800 with fix
The fix uniques the bundle of getelementptr indices we are about to vectorize
since it's possible for the same index to be used by multiple instructions.
The original commit message is below.

[SLP] Vectorize the index computations of getelementptr instructions.

This patch seeds the SLP vectorizer with getelementptr indices. The primary
motivation in doing so is to vectorize gather-like idioms beginning with
consecutive loads (e.g., g[a[0] - b[0]] + g[a[1] - b[1]] + ...). While these
cases could be vectorized with a top-down phase, seeding the existing bottom-up
phase with the index computations avoids the complexity, compile-time, and
phase ordering issues associated with a full top-down pass. Only bundles of
single-index getelementptrs with non-constant differences are considered for
vectorization.

llvm-svn: 257918
2016-01-15 18:51:51 +00:00
Reid Kleckner
47f2452da8 # This is a combination of 2 commits.
# The first commit's message is:

Revert "[ARM] Add DSP build attribute and extension targeting"

This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc.

# This is the 2nd commit message:

Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline"

This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5.

llvm-svn: 257916
2016-01-15 18:31:29 +00:00
Rafael Espindola
79db917139 Don't try to check all uses if lazy loading.
This means that LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN will not be set
in a few cases.

This should have no impact in ld64 since it doesn't use lazy loading
when merging modules and that is when it checks
LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN.

llvm-svn: 257915
2016-01-15 18:23:46 +00:00
George Rimar
06a9b6f5d1 Recommit r257912
Added forgotten ELFDumper.cpp to commit.

Initial commit message:
[llvm-readobj] Add support for TLSDESC_PLT and TLSDESC_GOT dynamic section tags to the llvm-readobj.

If module uses uses lazy TLSDESC relocations it should define DT_TLSDESC_PLT and DT_TLSDESC_GOT entries.
They were unknown for llvm-readobj before this patch.

Differential revision: http://reviews.llvm.org/D16224

llvm-svn: 257914
2016-01-15 18:21:34 +00:00