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Author SHA1 Message Date
Jim Grosbach
2597f83889 ARM: .end_data_region mismatch in Thumb2. 
32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221
 2012-05-21 23:34:42 +00:00
Jim Grosbach
4b63d2ae1d Refactor data-in-code annotations. 
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062
 2012-05-18 19:12:01 +00:00
Evan Cheng
48346c1cd9 Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676

llvm-svn: 154480
 2012-04-11 05:33:07 +00:00
Bob Wilson
6f9be7e2c6 Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543> 
The tLDRr instruction with the last register operand set to the zero register
prints in assembly as if no register was specified, and the assembler encodes
it as a tLDRi instruction with a zero immediate.  With the integrated assembler,
that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
is broken.  Emit the instruction as tLDRi with a zero immediate.  I don't
know if there's a good way to write a testcase for this.  Suggestions welcome.

Opportunities for follow-up work:
1) The asm printer should complain if a non-optional register operand is set
   to the zero register, instead of silently dropping it.
2) The integrated assembler should complain in the same situation, instead of
   silently emitting the operand as "r0".

llvm-svn: 154261
 2012-04-07 16:51:59 +00:00
Jim Grosbach
0c509fa6bf Tidy up. 80 columns. 
llvm-svn: 154226
 2012-04-06 23:43:50 +00:00
Jakob Stoklund Olesen
6a2e99a46a Deduplicate ARM call-related instructions. 
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.

llvm-svn: 154144
 2012-04-06 00:04:58 +00:00
Craig Topper
5fa0caafc0 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h 
llvm-svn: 153422
 2012-03-26 00:45:15 +00:00
Craig Topper
188ed9d56e Reorder includes to match coding standards. Fix an issue or two exposed by that. 
llvm-svn: 152978
 2012-03-17 07:33:42 +00:00
Sebastian Pop
957a6583f1 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00
Evan Cheng
65f9d19c4f Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. 
llvm-svn: 151645
 2012-02-28 18:51:51 +00:00
Daniel Dunbar
ee7b899343 Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. 
llvm-svn: 151630
 2012-02-28 15:36:07 +00:00
Evan Cheng
87c7b09d8d Some ARM implementaions, e.g. A-series, does return stack prediction. That is, 
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
 2012-02-28 06:42:03 +00:00
Evan Cheng
0460ae8d80 Proper support for a bastardized darwin-eabi hybird ABI. 
llvm-svn: 151083
 2012-02-21 20:46:00 +00:00
Bill Wendling
dfb45f4d68 Strip the pointer casts from the constants here. 
The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>

llvm-svn: 150572
 2012-02-15 09:14:08 +00:00
Craig Topper
e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
James Molloy
6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
 2012-01-26 09:25:43 +00:00
Chandler Carruth
ed975232bc Revert r148686 (and r148694, a fix to it) due to a serious layering 
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
 2012-01-24 00:30:17 +00:00
NAKAMURA Takumi
28ea8f523b ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here. 
llvm-svn: 148694
 2012-01-23 09:14:42 +00:00
Anton Korobeynikov
5482b9f535 Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
David Blaikie
46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Evgeniy Stepanov
4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. 
llvm-svn: 148473
 2012-01-19 12:53:06 +00:00
David Blaikie
edbb58c577 Remove unnecessary default cases in switches that cover all enum values. 
llvm-svn: 147855
 2012-01-10 16:47:17 +00:00
Bob Wilson
fadc2c83e5 Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006> 
These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417
 2011-12-12 21:45:15 +00:00
Evan Cheng
7f8e563a69 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen
2e05db2fa0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Nick Lewycky
50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Benjamin Kramer
20baffb257 Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
llvm-svn: 143891
 2011-11-06 20:37:06 +00:00
Owen Anderson
0ca562ec4c Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Bill Wendling
4a4772fae2 Use the ARMConstantPoolMBB class to handle the MBB values. 
llvm-svn: 140943
 2011-10-01 09:30:42 +00:00
Bill Wendling
c214cb055d Use the new ARMConstantPoolSymbol class to handle external symbols. 
llvm-svn: 140939
 2011-10-01 08:58:29 +00:00
Bill Wendling
7753d66468 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Bill Wendling
69bc3de4fc Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
llvm-svn: 140824
 2011-09-29 23:50:42 +00:00
Andrew Trick
924123acb3 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
 2011-09-21 02:20:46 +00:00
Owen Anderson
29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Jim Grosbach
05dec8b122 Tidy up. Formatting. 
llvm-svn: 139024
 2011-09-02 18:46:15 +00:00
Jim Grosbach
e1995f2566 Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Evan Cheng
2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Jim Grosbach
51b554247d Move ARM frame-unwinding EHABI handling a touch earlier. 
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

llvm-svn: 138386
 2011-08-23 21:32:34 +00:00
Rafael Espindola
36a3abc671 Add support for the R and Q constraints. 
llvm-svn: 137217
 2011-08-10 16:26:42 +00:00
Renato Golin
faff512536 Emitting ARM build attributes and values as ULEB, rather than char. 
llvm-svn: 137115
 2011-08-09 09:50:10 +00:00
Owen Anderson
2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. 
llvm-svn: 136141
 2011-07-26 20:54:26 +00:00
Evan Cheng
61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration. 
llvm-svn: 135974
 2011-07-25 21:20:24 +00:00
Evan Cheng
a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Jim Grosbach
204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. 
llvm-svn: 134734
 2011-07-08 20:39:19 +00:00
Jim Grosbach
4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. 
llvm-svn: 134732
 2011-07-08 20:32:21 +00:00
Jim Grosbach
dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls. 
llvm-svn: 134719
 2011-07-08 18:50:22 +00:00
Jim Grosbach
2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. 
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
 2011-07-08 18:15:12 +00:00
Jim Grosbach
95dee40343 Use TableGen'erated pseudo lowering for ARM. 
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
 2011-07-08 17:40:42 +00:00
Cameron Zwarich
148220306f The VMLA instruction and its friends are not actually fused; they're plain old 
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
 2011-07-07 08:28:52 +00:00
Evan Cheng
ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore. 
llvm-svn: 134525
 2011-07-06 19:45:42 +00:00
Jim Grosbach
e9cc901814 Refact ARM Thumb1 tMOVr instruction family. 
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
 2011-06-30 23:38:17 +00:00
Jim Grosbach
b98ab91e39 Thumb1 register to register MOV instruction is predicable. 
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
 2011-06-30 22:10:46 +00:00
Jim Grosbach
353da73186 Pseudo-ize the t2LDMIA_RET instruction. 
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173
 2011-06-30 18:25:42 +00:00
Jim Grosbach
417671a7b1 Pseudo-ize the Thumb tPOP_RET instruction. 
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172
 2011-06-30 17:34:04 +00:00
Jim Grosbach
a8a8067dec Remove redundant Thumb2 ADD/SUB SP instruction definitions. 
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.

llvm-svn: 134114
 2011-06-29 23:25:04 +00:00
Eric Christopher
d00e8ad803 Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
 2011-05-28 01:40:44 +00:00
Rafael Espindola
d23bfb8a7a Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00
Eric Christopher
33a73c7755 Reorganize these slightly according to operand type. 
llvm-svn: 132128
 2011-05-26 18:22:26 +00:00
Cameron Zwarich
26ddb12118 Mark tBX as an indirect branch rather than a return. 
llvm-svn: 132107
 2011-05-26 03:41:12 +00:00
Cameron Zwarich
a946f476d3 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
llvm-svn: 132086
 2011-05-25 21:53:50 +00:00
Eric Christopher
8c5e4192e6 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939

llvm-svn: 132081
 2011-05-25 20:51:58 +00:00
Cameron Zwarich
3088e0a179 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

llvm-svn: 132042
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
deaf994ff0 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Eric Christopher
1b724948e9 Implement the arm 'L' asm modifier. 
Part of rdar://9119939

llvm-svn: 132024
 2011-05-24 23:27:13 +00:00
Eric Christopher
b1dda56ac2 Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939

llvm-svn: 132023
 2011-05-24 23:15:43 +00:00
Eric Christopher
d4562566b4 Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.

llvm-svn: 132015
 2011-05-24 22:27:43 +00:00
Eric Christopher
7617883ce3 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657

llvm-svn: 132011
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
bc90690b24 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

llvm-svn: 131894
 2011-05-23 01:57:17 +00:00
Rafael Espindola
652bfdb1ab adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
 2011-05-20 20:10:34 +00:00
Rafael Espindola
e90c1cb221 sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

llvm-svn: 131406
 2011-05-16 16:17:21 +00:00
Devang Patel
39ecf816c5 Do not emit location expression size twice. 
llvm-svn: 130854
 2011-05-04 19:00:57 +00:00
Devang Patel
3e021533cd Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373
 2011-04-28 02:22:40 +00:00
Devang Patel
e3745fdcf3 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
llvm-svn: 130326
 2011-04-27 20:29:27 +00:00
Devang Patel
cae2fbd6fc Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
llvm-svn: 130178
 2011-04-26 00:12:46 +00:00
Devang Patel
3c39ec2933 Add asserts. 
llvm-svn: 129995
 2011-04-22 16:44:29 +00:00
Devang Patel
94ad6ac13c Fix DWARF description of Q registers. 
llvm-svn: 129952
 2011-04-21 23:22:35 +00:00
Devang Patel
3712c14be9 Fix DWARF description of S registers. 
llvm-svn: 129947
 2011-04-21 22:48:26 +00:00
Chris Lattner
0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Bill Wendling
00f0cddfd4 We need to pass the TargetMachine object to the InstPrinter if we are printing 
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.

llvm-svn: 127986
 2011-03-21 04:13:46 +00:00
Jim Grosbach
3af6fe66b9 Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches. 
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

llvm-svn: 127637
 2011-03-15 00:30:40 +00:00
Jim Grosbach
3f2096eafe Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same 
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

llvm-svn: 127515
 2011-03-12 00:45:26 +00:00
Jim Grosbach
f026d9ed53 Pseudo-ize the ARM 'B' instruction. 
llvm-svn: 127510
 2011-03-11 23:24:15 +00:00
Jim Grosbach
6d371ce37e Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- 
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
 2011-03-11 22:51:41 +00:00
Anton Korobeynikov
692f633df9 ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case 
llvm-svn: 127106
 2011-03-05 18:44:00 +00:00
Anton Korobeynikov
9e66cbb366 In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. 
llvm-svn: 127105
 2011-03-05 18:43:55 +00:00
Anton Korobeynikov
a8d177b2d4 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. 
llvm-svn: 127104
 2011-03-05 18:43:50 +00:00
Anton Korobeynikov
51537f1c7f Add unwind information emission for thumb stuff 
llvm-svn: 127103
 2011-03-05 18:43:43 +00:00
Anton Korobeynikov
e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags. 
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
 2011-03-05 18:43:32 +00:00
Renato Golin
e84af17b6e Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard. 
llvm-svn: 126882
 2011-03-02 21:20:09 +00:00
Renato Golin
ec0fc7d842 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931 
llvm-svn: 126689
 2011-02-28 22:04:27 +00:00
Jason W Kim
e5ce4c9bcd ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .o 
llvm-svn: 125025
 2011-02-07 19:07:11 +00:00
Jason W Kim
85b0af177f Rework some .ARM.attribute work for improved gcc compatibility. 
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.

llvm-svn: 124995
 2011-02-07 00:49:53 +00:00
Evan Cheng
2f2435d026 Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
 2011-01-21 18:55:51 +00:00
Evan Cheng
dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Jason W Kim
e9eae0f887 JimG sez: "The value-kinds look like masks, but they're not consistently used 
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340
 2011-01-12 23:21:49 +00:00
Jason W Kim
9c5b65d289 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
 2011-01-12 00:19:25 +00:00
Evan Cheng
e45d685895 Clean up ARM subtarget code by using Triple ADT. 
llvm-svn: 123276
 2011-01-11 21:46:47 +00:00
Anton Korobeynikov
62acecd7e1 Model operand restrictions of mul-like instructions on ARMv5 via 
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

llvm-svn: 122663
 2011-01-01 20:38:38 +00:00
Bill Wendling
429bb1e2cc r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to 
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
 2010-12-18 02:13:59 +00:00
Bob Wilson
a7dabbd2cf Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
 2010-12-17 23:06:42 +00:00
Jim Grosbach
b5743b9d76 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Jim Grosbach
509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Jim Grosbach
8c1fabe367 Refactor a bit for legibility. 
llvm-svn: 121790
 2010-12-14 21:10:47 +00:00
Jim Grosbach
96254146cf Make sure to propagate the predicate operands for LEApcrel to ADR. 
llvm-svn: 121788
 2010-12-14 20:45:47 +00:00
Bill Wendling
092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Owen Anderson
6d375e5637 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.

llvm-svn: 121735
 2010-12-14 00:36:49 +00:00
Jim Grosbach
6233189713 Add a textual message to the assert. 
llvm-svn: 121349
 2010-12-09 01:23:51 +00:00
Jim Grosbach
ed40288eb4 Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are 
referencing the stack pointer as they say they are.

llvm-svn: 121347
 2010-12-09 01:22:19 +00:00
Jim Grosbach
ce2bd8d05f Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Jim Grosbach
dc35e067c1 Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Jim Grosbach
d0d1329fc8 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Jim Grosbach
3b4e2ab5f3 Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Jim Grosbach
cd5e30f6c6 Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Bill Wendling
8294a30d54 s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Jim Grosbach
7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Jim Grosbach
81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Jim Grosbach
58bc36a3a9 ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Jim Grosbach
150b1ad7f8 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Jim Grosbach
08c562bba6 Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly 
in the MC lowering process.

llvm-svn: 119559
 2010-11-17 21:05:55 +00:00
Jim Grosbach
5cf10ea1d1 Add FIXMEs. 
llvm-svn: 119167
 2010-11-15 18:36:48 +00:00
Chris Lattner
63274cbc5d add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Chris Lattner
de16ca8ecc rename LowerToMCInst -> LowerARMMachineInstrToMCInst. 
llvm-svn: 119071
 2010-11-14 21:00:02 +00:00
Chris Lattner
c5afd12557 even more simplifications. ARM MCInstLowering is now just 
a single function instead of a class.  It doesn't need the
complexity that X86 does.

llvm-svn: 119070
 2010-11-14 20:58:38 +00:00
Chris Lattner
b28e691657 simplify and tidy up 
llvm-svn: 119066
 2010-11-14 20:31:06 +00:00
Jim Grosbach
ca21cd749e Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

llvm-svn: 118688
 2010-11-10 17:59:10 +00:00
Jim Grosbach
f23b2d9d8d Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623

llvm-svn: 118671
 2010-11-10 03:26:07 +00:00
Jim Grosbach
a942ad4222 Change the ARMConstantPoolValue modifier string to an enumeration. This will 
help in MC'izing the references that use them.

llvm-svn: 118633
 2010-11-09 21:36:17 +00:00
Jim Grosbach
2fd4c37d8b Handle ARM constant pool values that need an explicit reference to the '.' 
pseudo-label. (TLS stuff).

llvm-svn: 118609
 2010-11-09 19:40:22 +00:00
Jim Grosbach
38f8e76e51 Further MCize ARM constant pool values. This allows basic PIC references for 
object file emission.

llvm-svn: 118601
 2010-11-09 18:45:04 +00:00
Dale Johannesen
0ef474730f Revert 118422 in search of bot verdancy. 
llvm-svn: 118429
 2010-11-08 19:17:22 +00:00
Jason W Kim
f3e224f830 Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. 
llvm-svn: 118422
 2010-11-08 17:58:07 +00:00
Jim Grosbach
5a2c68d308 MC'ize the '.code 16' and '.thumb_func' ARM directives. 
llvm-svn: 118301
 2010-11-05 22:08:08 +00:00
Jim Grosbach
ff9e507d8e MC'ize simple ARMConstantValue entry emission (with a FIXME). 
llvm-svn: 118295
 2010-11-05 20:34:24 +00:00
Jim Grosbach
1df82e67d1 Add FIXME. 
llvm-svn: 118280
 2010-11-05 17:37:13 +00:00
Jim Grosbach
4a0c2d73c3 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Jim Grosbach
e477b1ad30 ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

llvm-svn: 117707
 2010-10-29 20:37:06 +00:00
Jim Grosbach
338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach
5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach
1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Rafael Espindola
d9d0c348df Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00
Rafael Espindola
752913d6ba Add a virtual destructor. 
llvm-svn: 117280
 2010-10-25 18:38:32 +00:00
Rafael Espindola
0ed1543d4e Add support for emitting ARM file attributes. 
llvm-svn: 117275
 2010-10-25 17:50:35 +00:00
Jason W Kim
109ff296c8 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
 2010-10-11 23:01:44 +00:00
Jim Grosbach
25cd3bfbd7 remove trailing whitespace 
llvm-svn: 115860
 2010-10-06 22:46:47 +00:00
Jason W Kim
bff84d418f First in a sequence of ARM/MC/*ELF* specific work. 
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859
 2010-10-06 22:36:46 +00:00
Jim Grosbach
f49540cb4f Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
llvm-svn: 115845
 2010-10-06 21:36:43 +00:00
Jim Grosbach
2c95027258 Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed 
"lane" operand modifier.

llvm-svn: 115843
 2010-10-06 21:22:32 +00:00
Jim Grosbach
8025f89860 target operand flag values aren't a bitmask 
llvm-svn: 115798
 2010-10-06 16:51:55 +00:00
Jim Grosbach
fae8305e2b Nuke the rest of the :comment references 
llvm-svn: 115373
 2010-10-01 23:21:38 +00:00
Jim Grosbach
0e854f3d43 Rename the AsmPrinter directory to InstPrinter for those targets that have 
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.

llvm-svn: 115360
 2010-10-01 22:39:28 +00:00
Jim Grosbach
c8e2e9d830 Nuke a few more unused asm strings 
llvm-svn: 115193
 2010-09-30 19:53:58 +00:00
Jim Grosbach
136ed51b08 80 column fix 
llvm-svn: 115149
 2010-09-30 15:25:22 +00:00
Jason W Kim
645f6c2bef Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile() 
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.

llvm-svn: 115133
 2010-09-30 02:45:56 +00:00
Jim Grosbach
080fdf4609 Nuke it from orbit. It's the only way to be sure. 
(Kill the dead non-MC asm printer for the ARM target.)

llvm-svn: 115127
 2010-09-30 01:57:53 +00:00
Jim Grosbach
05eccf0e44 One Printer to rule them all, One Printer to find them, 
One Printer to lower them all and in the back end bind them.


(Remove option to use the old non-MC asm printer.)

llvm-svn: 115038
 2010-09-29 15:23:40 +00:00
Jim Grosbach
45c83d496f Factor out dbg_value comment printing and teach MC asm printing to use it. 
This should make the arm-linux self-host buildbot happy again.

llvm-svn: 114964
 2010-09-28 17:05:56 +00:00
Jim Grosbach
175d6411c8 Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to 
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

llvm-svn: 114915
 2010-09-27 22:28:11 +00:00
Jim Grosbach
9e9ed98305 ARM-mode eh.sjlj.longjmp MC lowering 
llvm-svn: 114896
 2010-09-27 21:47:04 +00:00
Jim Grosbach
11fed543c9 Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to 
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

llvm-svn: 114892
 2010-09-27 21:28:44 +00:00
Jim Grosbach
4a6ab13fb9 Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence. 
llvm-svn: 114758
 2010-09-24 20:47:58 +00:00
Jim Grosbach
c0aed7179a ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion 
llvm-svn: 114707
 2010-09-23 23:33:56 +00:00
Jim Grosbach
7d34837676 never mind. I can't read, apparently 
llvm-svn: 114689
 2010-09-23 19:42:17 +00:00
Jim Grosbach
836341a17a Fix opcode value for the 'trap' instruction, keeping the type suffix on the 
constant. Hopefully the non-Darwin bots will like it...

llvm-svn: 114687
 2010-09-23 19:32:40 +00:00
Jim Grosbach
3d50a3e237 explicit 'unsigned long' on constant value. Hopefully make bots happier. 
llvm-svn: 114686
 2010-09-23 19:08:04 +00:00
Benjamin Kramer
e38495dbc0 Unbreak build. Jim, please review. 
llvm-svn: 114684
 2010-09-23 18:57:26 +00:00
Jim Grosbach
8503054410 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

llvm-svn: 114679
 2010-09-23 18:05:37 +00:00
Jim Grosbach
1f57cc4a59 add FIXME 
llvm-svn: 114578
 2010-09-22 20:55:15 +00:00
Jim Grosbach
284eebc1ae Add MC instruction printer support for ARM and Thumb1 jump tables. 
llvm-svn: 114555
 2010-09-22 17:39:48 +00:00
Jim Grosbach
1573b29ea7 Add MC instruction printer support for TB[BH] style thumb2 jump tables. 
llvm-svn: 114553
 2010-09-22 17:15:35 +00:00
Jim Grosbach
754e1efffc Clean up comment. 
llvm-svn: 114550
 2010-09-22 16:45:13 +00:00
Jim Grosbach
d64f9b8381 Add start of support for MC instruction printer of ARM jump tables. Filling in 
the rest of it is next up.

llvm-svn: 114500
 2010-09-21 23:28:16 +00:00
Jim Grosbach
cbac342e1a Fix errant printing of [v]ldm instructions that aren't a pop 
llvm-svn: 114445
 2010-09-21 16:45:31 +00:00
Jim Grosbach
af5d63583e factor out a simple helper function to create a label for PC-relative 
instructions (PICADD, PICLDR, et.al.)

llvm-svn: 114243
 2010-09-18 00:05:05 +00:00
Jim Grosbach
3d97920829 Add MC-inst handling for tPICADD 
llvm-svn: 114237
 2010-09-17 23:41:53 +00:00
Jim Grosbach
7a6c37d3e7 Teach the (non-MC) instruction printer to use the cannonical names for push/pop, 
and shift instructions on ARM. Update the tests to match.

llvm-svn: 114230
 2010-09-17 22:36:38 +00:00
Jim Grosbach
132a0ce787 Hook up verbose asm comment printing for SOImm operands in MC printer 
llvm-svn: 114215
 2010-09-17 21:33:25 +00:00
Jim Grosbach
0d35df1cfe handle the upper16/lower16 target operand flags on symbol references for MC 
instruction lowering.

llvm-svn: 114191
 2010-09-17 18:25:25 +00:00
Jim Grosbach
a7d430b51c expand PICLDR MC lowering to handle other PICLDR and PICSTR versions. 
llvm-svn: 114183
 2010-09-17 16:25:52 +00:00
Jim Grosbach
218e22da8b MC-ization of the PICLDR pseudo. Next up, adding the other variants 
(PICLDRB, et. al.) and PICSTR*

llvm-svn: 114098
 2010-09-16 17:43:25 +00:00
Bob Wilson
a625b0110b Remove support for "dregpair" operand modifier, now that it is no longer being 
used for anything.

llvm-svn: 114067
 2010-09-16 04:55:00 +00:00
Jim Grosbach
40e85fbf17 move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper 
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

llvm-svn: 114016
 2010-09-15 20:26:25 +00:00
Jim Grosbach
a244f70113 Add predicate and 's' bit operands to PICADD instruction lowering. 
llvm-svn: 113860
 2010-09-14 21:28:17 +00:00
Jim Grosbach
7ae94222cd fix comment typo 
llvm-svn: 113856
 2010-09-14 21:05:34 +00:00
Jim Grosbach
8ee5cd99ef Remove trailing whitespace 
llvm-svn: 112790
 2010-09-02 01:02:06 +00:00
Bob Wilson
13ce07fa92 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like 
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322
 2010-08-27 23:18:17 +00:00
Bob Wilson
481d7a9ab4 Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168
 2010-08-16 18:27:34 +00:00
Johnny Chen
8e8f1c133a Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Bob Wilson
add513112a Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Bob Wilson
97886d59d1 ARM "rrx" shift operands do not have an immediate. PR7790. 
llvm-svn: 110292
 2010-08-05 00:34:42 +00:00
Devang Patel
a52ddc496a Implement target specific getDebugValueLocation(). 
llvm-svn: 110267
 2010-08-04 22:39:39 +00:00
Bob Wilson
b128824b60 Move newlines before inline jumptables from the asm strings in .td files to 
the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948
 2010-07-31 06:28:10 +00:00
Bob Wilson
4320e2d1bb Add the __TEXT,__StaticInit section to the list of sections emitted at the 
beginning on ARM Darwin assembly files so that it won't be placed after
debug sections.  Radar 8252813.

llvm-svn: 109879
 2010-07-30 19:55:47 +00:00
Jim Grosbach
965a73a28c For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb 
rdar://8202967

llvm-svn: 109057
 2010-07-21 23:03:52 +00:00
Chris Lattner
b792b463af sink the arm implementations of ASmPrinter and MCInstLower 
out of the AsmPrinter directory into libarm.  Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.

llvm-svn: 108783
 2010-07-19 23:44:46 +00:00
Anton Korobeynikov
17d28de8ac Move ARM to pluggable asmprinter 
llvm-svn: 54889
 2008-08-17 13:55:10 +00:00
Anton Korobeynikov
ed47329174 Handle visibility printing with all generality. Remove bunch of duplicate code. 
llvm-svn: 54540
 2008-08-08 18:25:07 +00:00
Evan Cheng
df8c7faf60 Undo most of r54519. 
llvm-svn: 54534
 2008-08-08 17:56:50 +00:00
Evan Cheng
655fa0fec4 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 
llvm-svn: 54519
 2008-08-08 06:56:16 +00:00
Anton Korobeynikov
04083529df Switch ARM to new section handling stuff 
llvm-svn: 54458
 2008-08-07 09:54:23 +00:00
Dale Johannesen
c4650f4b56 Emit debug info for data-only files. ARM version. 
llvm-svn: 53360
 2008-07-09 21:20:54 +00:00
Evan Cheng
49c8e68e4c Back out 53254. It broke ppc debug info codegen. 
llvm-svn: 53280
 2008-07-09 06:36:53 +00:00
Dale Johannesen
b9097a71d4 Make debug info come out in data-only files. 
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254
 2008-07-08 21:56:22 +00:00
Dan Gohman
c7fc432b19 Minor const-correctness fixes. 
llvm-svn: 53196
 2008-07-07 20:06:06 +00:00
Dale Johannesen
5bf742f2aa Handle quoted names when constructing $stub's, 
$non_lazy_ptr's and $lazy_ptr's.

llvm-svn: 51277
 2008-05-19 21:38:18 +00:00
Evan Cheng
c799065cc3 Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 
llvm-svn: 47703
 2008-02-28 00:43:03 +00:00
Bill Wendling
c24ea4fb41 Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 
would have been a Godsend here!

llvm-svn: 47625
 2008-02-26 21:11:01 +00:00
Chris Lattner
7b1431785b Handle \n's in value names for more targets. The asm printers 
really really really need refactoring :(

llvm-svn: 47171
 2008-02-15 19:04:54 +00:00
Dale Johannesen
ffde4ff5b1 __DATA not __DATA__ is the right segment name on darwin. 
Spotted by Nick Kledzik.

llvm-svn: 47037
 2008-02-12 23:35:09 +00:00
Dan Gohman
3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Evan Cheng
32e5347eb8 Get rid of the annoying blank lines before labels. 
llvm-svn: 46667
 2008-02-02 08:39:46 +00:00
Bill Wendling
96a1b810ec If the function has no machine instructions, then emit a "nop" so that 
the function label isn't associated with something it shouldn't be.

llvm-svn: 46449
 2008-01-28 09:15:03 +00:00
Dale Johannesen
7f1ff5fedd Honor explicit section information on Darwin. 
llvm-svn: 46267
 2008-01-23 00:58:14 +00:00
Dale Johannesen
8ef89eabc2 Revert the part of 45849 that treated weak globals 
as weak globals rather than commons.  While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.

llvm-svn: 46147
 2008-01-17 23:36:04 +00:00
Dale Johannesen
193daf0698 Weak zeroes don't go in bss on Darwin. 
llvm-svn: 45849
 2008-01-11 01:59:45 +00:00
Chris Lattner
a5bb370aa4 Add new shorter predicates for testing machine operands for various types: 
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
 2007-12-30 23:10:15 +00:00
Chris Lattner
5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm 
llvm-svn: 45453
 2007-12-30 20:49:49 +00:00
Chris Lattner
f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
797d56ff17 Much improved pic jumptable codegen: 
Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924
 2007-11-09 01:32:10 +00:00
Lauro Ramos Venancio
1a30c18e88 [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
 2007-11-05 18:33:37 +00:00
Duncan Sands
283207a71c Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Evan Cheng
cdf3609130 Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dan Gohman
dc35bd79ca Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Dan Gohman
c731c97fac Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Gordon Henriksen
0b7cf862bc AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng
1ff71872c2 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Dan Gohman
cf0a5349de Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Evan Cheng
0a42fdf346 Print the s bit if the instruction is toggled to its CPSR setting form. 
llvm-svn: 37932
 2007-07-06 01:01:34 +00:00
Dale Johannesen
485531ea9b Quote complex names for Darwin X86 and ARM. 
llvm-svn: 37700
 2007-06-22 00:54:56 +00:00
Evan Cheng
5c48958a61 Print predicate of the second instruction of the two-piece constant MI. 
llvm-svn: 37437
 2007-06-05 18:55:18 +00:00
Evan Cheng
252695f0f6 PIC label asm printing cosmetic changes. 
llvm-svn: 37434
 2007-06-05 07:36:38 +00:00
Chris Lattner
3e3ff30aa2 Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373
 2007-05-31 18:57:45 +00:00
Evan Cheng
0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng
9c031c0ddf Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Evan Cheng
23040754b0 Should never see an indexed load / store with zero offset. 
llvm-svn: 36714
 2007-05-03 23:30:36 +00:00
Lauro Ramos Venancio
83930198dd Debug support for arm-linux. 
Patch by Raul Herbster.

llvm-svn: 36690
 2007-05-03 20:28:35 +00:00
Chris Lattner
9a8c7cf00b add support for printing offset from global 
llvm-svn: 36669
 2007-05-03 16:42:23 +00:00
Lauro Ramos Venancio
2c673ad7ef Enable protected visibility on ARM. 
llvm-svn: 36583
 2007-04-30 00:23:51 +00:00
Lauro Ramos Venancio
c39c12a3fa ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Lauro Ramos Venancio
4ae9425bb6 remember to emit weak reference in one more case. 
llvm-svn: 36438
 2007-04-25 14:50:40 +00:00
Dale Johannesen
ed0ecdb7ff add Align field, and use when generating function alignment 
llvm-svn: 36371
 2007-04-23 20:07:25 +00:00
Lauro Ramos Venancio
ee2d164f0f Implement PIC for arm-linux. 
llvm-svn: 36324
 2007-04-22 00:04:12 +00:00
Evan Cheng
1e150dedd1 Implement inline asm modifier P. 
llvm-svn: 35640
 2007-04-04 00:13:29 +00:00
Evan Cheng
8f592160c0 Add support for hidden visibility to darwin/arm. 
llvm-svn: 35448
 2007-03-29 07:49:34 +00:00
Evan Cheng
9e7b838469 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
ea28fc5dc4 Implement inline asm modifier c. 
llvm-svn: 35035
 2007-03-08 22:42:46 +00:00
Evan Cheng
ddf082082c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Evan Cheng
d918477ac3 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.

llvm-svn: 35017
 2007-03-08 01:25:25 +00:00
Bill Wendling
65c75b57d4 Get rid of verboten <iostream> include. 
llvm-svn: 34777
 2007-03-01 06:05:39 +00:00
Lauro Ramos Venancio
903e01d407 Fix .thumb_func directive on linux. 
llvm-svn: 33759
 2007-02-01 18:25:34 +00:00
Evan Cheng
ed81dea45b Don't emit unnecessary .align directive. 
llvm-svn: 33729
 2007-01-31 23:39:39 +00:00
Evan Cheng
83f35170fa - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Reid Spencer
5301e7c605 For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid 
confusion with external linkage types.

llvm-svn: 33663
 2007-01-30 20:08:39 +00:00
Evan Cheng
0e083d0161 Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections. 
llvm-svn: 33657
 2007-01-30 08:04:53 +00:00
Evan Cheng
1cd3c0efb8 Change the operand orders to t_addrmode_s* to make it easier to morph 
instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651
 2007-01-30 02:35:32 +00:00
Evan Cheng
0701c5a074 Thumb jumptable support. 
llvm-svn: 33568
 2007-01-27 02:29:45 +00:00
Jim Laskey
c56315c2b5 Change the MachineDebugInfo to MachineModuleInfo to better reflect usage 
for debugging and exception handling.

llvm-svn: 33550
 2007-01-26 21:22:28 +00:00
Lauro Ramos Venancio
aa26c1ab9d If the constant pool value is a extern weak symbol, emit the weak reference. 
llvm-svn: 33543
 2007-01-26 19:51:32 +00:00
Lauro Ramos Venancio
4f7d37fe04 Fix elf object definition. 
llvm-svn: 33502
 2007-01-25 20:11:04 +00:00
Evan Cheng
c1a1bd18e3 Getting rid uses of evil std::set<> 
llvm-svn: 33496
 2007-01-25 03:07:27 +00:00
Evan Cheng
c0b7366cf9 - Reorg Thumb load / store instructions. Combine each rr and ri pair of 
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.

llvm-svn: 33470
 2007-01-23 22:59:13 +00:00
Evan Cheng
1199c2d653 Restructure code a bit to make use of continue (simplifying things). Generalize 
the .zerofill directive emission to not be darwin-specific.

llvm-svn: 33365
 2007-01-19 19:25:36 +00:00
Lauro Ramos Venancio
75aaf1fa6a Fix section definition. 
llvm-svn: 33359
 2007-01-19 17:33:22 +00:00
Evan Cheng
10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Chris Lattner
5cfa5ef912 Fix for ARM weak symbols, patch by Lauro Ramos Venancio! 
llvm-svn: 32740
 2006-12-21 22:59:58 +00:00
Chris Lattner
1ef9cd400d eliminate static ctors for Statistic objects. 
llvm-svn: 32703
 2006-12-19 22:59:26 +00:00
Rafael Espindola
d7998d0e6d move ExtWeakSymbols to AsmPrinter 
llvm-svn: 32648
 2006-12-18 03:37:18 +00:00
Rafael Espindola
b8ada08b26 .align is in bits 
.comm is in bytes
:-(

llvm-svn: 32408
 2006-12-10 02:53:14 +00:00
Rafael Espindola
d12d2250a7 %progbits not @progbits 
llvm-svn: 32376
 2006-12-08 22:06:02 +00:00
Rafael Espindola
94f29f129d add \"aw\",@progbits" to ctors and dtors 
llvm-svn: 32373
 2006-12-08 21:24:58 +00:00
Rafael Espindola
265fa68bd8 fix alignment 
llvm-svn: 32337
 2006-12-07 22:38:06 +00:00
Bill Wendling
9bfb1e1f29 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Rafael Espindola
219a796475 make sure that we don't use a common symbol if a section was specified 
llvm-svn: 32310
 2006-12-07 18:33:58 +00:00
Chris Lattner
700b873130 Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Rafael Espindola
776abee608 print weak references 
llvm-svn: 32276
 2006-12-06 13:35:10 +00:00
Chris Lattner
81cf22d873 These asm printers shouldn't use assembly/writer.h 
llvm-svn: 32262
 2006-12-06 06:13:25 +00:00
Rafael Espindola
2369a024d7 add support for weak linkage 
llvm-svn: 32222
 2006-12-05 17:00:17 +00:00
Rafael Espindola
5f7ab1b964 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Rafael Espindola
708cb60588 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Rafael Espindola
ac8668d62f move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall

llvm-svn: 31378
 2006-11-02 15:00:02 +00:00
Rafael Espindola
3576405a26 print null values in bss 
llvm-svn: 31349
 2006-11-01 14:26:44 +00:00
Rafael Espindola
ea67b973c2 print common symbols 
llvm-svn: 31048
 2006-10-19 13:30:40 +00:00
Rafael Espindola
19398ec86e initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola
f719c5f43d expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Chris Lattner
a6a570e02f Pass the MachineFunction into EmitJumpTableInfo. 
llvm-svn: 30742
 2006-10-05 03:01:21 +00:00
Chris Lattner
4431699187 Use getSectionForFunction. 
llvm-svn: 30740
 2006-10-05 02:49:23 +00:00
Rafael Espindola
3130a756ef add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Rafael Espindola
e45a79a9e2 partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
ecb0d686f8 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
llvm-svn: 30246
 2006-09-11 12:49:38 +00:00
Anton Korobeynikov
fbee8bfe48 Removed unnecessary Mangler creation. 
llvm-svn: 30239
 2006-09-10 21:17:03 +00:00
Jim Laskey
261779bb45 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Jim Laskey
a6211dcdad Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Rafael Espindola
98dc23fd1f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Rafael Espindola
fe03fe9bf4 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola
e08b9853cc initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Rafael Espindola
c3ed77e1b9 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Rafael Espindola
8b7bd8264b start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola
95035cf001 implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Rafael Espindola
7cc2d19fc1 handle GlobalValue::InternalLinkage in doFinalization 
llvm-svn: 29417
 2006-07-31 20:38:13 +00:00
Rafael Espindola
89e5cbd897 emit global constants 
llvm-svn: 29344
 2006-07-27 11:38:51 +00:00
Rafael Espindola
75269be065 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00