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70 Commits

Author SHA1 Message Date
Owen Anderson
721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Owen Anderson
ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Owen Anderson
b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Owen Anderson
96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson
192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson
5d2db89ba6 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
llvm-svn: 137997
 2011-08-18 22:15:25 +00:00
Owen Anderson
67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Jim Grosbach
d14b70d00b Tidy up. 80 columns. 
llvm-svn: 137881
 2011-08-17 21:58:18 +00:00
Jim Grosbach
46dd413991 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
 2011-08-17 21:51:27 +00:00
Owen Anderson
187e1e46f9 Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. 
llvm-svn: 137838
 2011-08-17 18:14:48 +00:00
Owen Anderson
a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Owen Anderson
91a8f9be20 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
llvm-svn: 137787
 2011-08-16 23:45:44 +00:00
Owen Anderson
a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Owen Anderson
1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson
b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson
2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson
60138eaf93 Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson
3987a61c16 Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Owen Anderson
c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Jim Grosbach
e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson
ff0b442330 Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson
2f7aa73312 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Owen Anderson
b685c9f011 Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Owen Anderson
3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson
6066340301 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Owen Anderson
3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Owen Anderson
0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson
ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach
d5d6359785 ARM LDRT assembly parsing and encoding. 
llvm-svn: 137282
 2011-08-10 23:43:54 +00:00
Owen Anderson
c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Owen Anderson
5d69f63bbb Cleanups based on Nick Lewycky's feedback. 
llvm-svn: 137224
 2011-08-10 17:36:48 +00:00
Owen Anderson
8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
llvm-svn: 137189
 2011-08-10 00:03:03 +00:00
Owen Anderson
92b942b1b5 Tighten operand checking of register-shifted-register operands. 
llvm-svn: 137180
 2011-08-09 23:33:27 +00:00
Owen Anderson
e008931bf6 Tighten operand checking on memory barrier instructions. 
llvm-svn: 137176
 2011-08-09 23:25:42 +00:00
Owen Anderson
3d2e0e9db6 Tighten operand checking on CPS instructions. 
llvm-svn: 137172
 2011-08-09 23:05:39 +00:00
Owen Anderson
042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
llvm-svn: 137168
 2011-08-09 22:48:45 +00:00
Benjamin Kramer
406dc1755f ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
 2011-08-09 22:02:50 +00:00
Owen Anderson
d151b09921 Silence an false-positive warning. 
llvm-svn: 137154
 2011-08-09 21:38:14 +00:00
Owen Anderson
7a2401dbf0 Tighten Thumb1 branch predicate decoding. 
llvm-svn: 137146
 2011-08-09 21:07:45 +00:00
Owen Anderson
e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Jim Grosbach
d359571120 ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
 2011-08-03 23:50:40 +00:00
Johnny Chen
dc62e59776 Fix typo in the comment. 
llvm-svn: 129837
 2011-04-19 23:58:52 +00:00
Kevin Enderby
9377a52c12 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Johnny Chen
923f3dac01 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen
02e59ad506 Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! 
llvm-svn: 128241
 2011-03-24 21:42:55 +00:00
Benjamin Kramer
dd9eb21c3f Plug a leak in the arm disassembler and put the tests back. 
llvm-svn: 128238
 2011-03-24 21:14:28 +00:00
Johnny Chen
7ca3ddc233 For ARM Disassembler, start a newline to dump the opcode and friends for an instruction. 
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.

llvm-svn: 128122
 2011-03-22 23:49:46 +00:00
Johnny Chen
9363d41f14 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354
 2011-03-09 20:01:14 +00:00
Owen Anderson
4ebf471c9b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. 
llvm-svn: 125127
 2011-02-08 22:39:40 +00:00