2 Commits

Author	SHA1	Message	Date
Tim Northover	e94a518a22	IR: add a second ordering operand to cmpxhg for failure ... The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559	2014-03-11 10:48:52 +00:00
Michael Kuperstein	661e288a70	Ensure bitcode encoding of instructions and their operands stays stable. ... This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls. Work was done by lama.saba@intel.com. llvm-svn: 202647	2014-03-02 15:26:36 +00:00