From 5a9ee6875d168f82e7680b1aa44a96a19bfb075e Mon Sep 17 00:00:00 2001 From: Gericom Date: Fri, 6 Mar 2020 00:17:17 +0100 Subject: [PATCH] Fixed more 16 bit byte related problems, fixed DL bug in reg to/from stack slot --- llvm/lib/CodeGen/CodeGenPrepare.cpp | 3 ++- .../SelectionDAG/SelectionDAGBuilder.cpp | 13 ++++++++++++ llvm/lib/MC/ELFObjectWriter.cpp | 15 ++++++++++--- .../Teak/MCTargetDesc/TeakAsmBackend.cpp | 6 +++--- .../Teak/MCTargetDesc/TeakMCCodeEmitter.cpp | 21 ++++++++++++++----- llvm/lib/Target/Teak/TeakISelLowering.cpp | 7 ++++++- llvm/lib/Target/Teak/TeakInstrInfo.cpp | 14 +++++++++---- 7 files changed, 62 insertions(+), 17 deletions(-) diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 34731d3836b..95fb0170f95 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -4265,7 +4265,8 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode, const StructLayout *SL = DL.getStructLayout(STy); unsigned Idx = cast(AddrInst->getOperand(i))->getZExtValue(); - ConstantOffset += SL->getElementOffset(Idx); + //TODO: Preferably detect the teak target here! + ConstantOffset += SL->getElementOffset(Idx) >> 1; } else { uint64_t TypeSize = DL.getTypeAllocSize(GTI.getIndexedType()); if (ConstantInt *CI = dyn_cast(AddrInst->getOperand(i))) { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 5a376775eaf..fbc383cc366 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -3864,11 +3864,13 @@ void SelectionDAGBuilder::visitExtractValue(const User &I) { } void SelectionDAGBuilder::visitGetElementPtr(const User &I) { + dbgs() << "visitGetElementPtr\n"; Value *Op0 = I.getOperand(0); // Note that the pointer operand may be a vector of pointers. Take the scalar // element which holds a pointer. unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace(); SDValue N = getValue(Op0); + N.dump(); SDLoc dl = getCurSDLoc(); auto &TLI = DAG.getTargetLoweringInfo(); MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS); @@ -3898,6 +3900,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { { assert((Offset & 1) == 0 && "Field offset is not word-aligned!"); Offset >>= 1; + dbgs() << "Offset >>= 1;\n"; } // In an inbounds GEP with an offset that is nonnegative even when @@ -3924,6 +3927,14 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { if (CI->isZero()) continue; APInt Offs = ElementSize * CI->getValue().sextOrTrunc(IdxSize); + if(TM.getTargetTriple().getArch() == Triple::teak) + { + assert((Offs & 1) == 0 && "Offs is not word-aligned!"); + dbgs() << "Offs = Offs.ashr(1);\n"; + dbgs() << Offs << "\n"; + Offs = Offs.ashr(1); + dbgs() << Offs << "\n"; + } LLVMContext &Context = *DAG.getContext(); SDValue OffsVal = VectorWidth ? DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorWidth)) : @@ -3999,6 +4010,8 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { if (PtrMemTy != PtrTy && !cast(I).isInBounds()) N = DAG.getPtrExtendInReg(N, dl, PtrMemTy); + DAG.dump(); + setValue(&I, N); } diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index 804f999a326..5cd0848d88c 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -1476,9 +1476,18 @@ void ELFObjectWriter::recordRelocation(MCAssembler &Asm, bool RelocateWithSymbol = shouldRelocateWithSymbol(Asm, RefA, SymA, C, Type); uint64_t Addend = 0; - FixedValue = !RelocateWithSymbol && SymA && !SymA->isUndefined() - ? C + Layout.getSymbolOffset(*SymA) - : C; + if (TargetObjectWriter->getEMachine() == ELF::EM_TEAK) + { + FixedValue = !RelocateWithSymbol && SymA && !SymA->isUndefined() + ? C + (Layout.getSymbolOffset(*SymA) >> 1) + : C; + } + else + { + FixedValue = !RelocateWithSymbol && SymA && !SymA->isUndefined() + ? C + Layout.getSymbolOffset(*SymA) + : C; + } if (hasRelocationAddend()) { Addend = FixedValue; FixedValue = 0; diff --git a/llvm/lib/Target/Teak/MCTargetDesc/TeakAsmBackend.cpp b/llvm/lib/Target/Teak/MCTargetDesc/TeakAsmBackend.cpp index d9a2f94b3dd..9dd7d595e33 100644 --- a/llvm/lib/Target/Teak/MCTargetDesc/TeakAsmBackend.cpp +++ b/llvm/lib/Target/Teak/MCTargetDesc/TeakAsmBackend.cpp @@ -123,11 +123,11 @@ void TeakAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, switch (Kind) { case Teak::fixup_teak_call_imm18: - write16le(&Data[Offset], (read16le(&Data[Offset]) & ~0x30) | (((Value >> 17) & 3) << 4)); - write16le(&Data[Offset + 2], (Value >> 1) & 0xFFFF); + write16le(&Data[Offset], (read16le(&Data[Offset]) & ~0x30) | (((Value >> 16) & 3) << 4)); + write16le(&Data[Offset + 2], Value & 0xFFFF); break; case Teak::fixup_teak_ptr_imm16: - write16le(&Data[Offset + 2], (Value >> 1) & 0xFFFF); + write16le(&Data[Offset + 2], Value); break; } // unsigned NumBytes = 4; diff --git a/llvm/lib/Target/Teak/MCTargetDesc/TeakMCCodeEmitter.cpp b/llvm/lib/Target/Teak/MCTargetDesc/TeakMCCodeEmitter.cpp index 57c992253bb..dbe3fb62cd5 100644 --- a/llvm/lib/Target/Teak/MCTargetDesc/TeakMCCodeEmitter.cpp +++ b/llvm/lib/Target/Teak/MCTargetDesc/TeakMCCodeEmitter.cpp @@ -304,11 +304,8 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, llvm_unreachable("Unsupported registers"); break; } - case Teak::AND_ab_ab_a: - EmitConstant(0x6770 - | (encodeAbOp(MI.getOperand(1).getReg()) << 2) - | (encodeAbOp(MI.getOperand(2).getReg()) << 0) - | (encodeAxOp(MI.getOperand(0).getReg()) << 12), 2, OS); + case Teak::ADD_regnobp016_a: + EmitConstant(0x86A0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS); break; case Teak::ADD_imm16_a: EmitConstant(0x86C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS); @@ -322,6 +319,12 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, EmitConstant(0x86E0 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS); EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS); break; + case Teak::AND_ab_ab_a: + EmitConstant(0x6770 + | (encodeAbOp(MI.getOperand(1).getReg()) << 2) + | (encodeAbOp(MI.getOperand(2).getReg()) << 0) + | (encodeAxOp(MI.getOperand(0).getReg()) << 12), 2, OS); + break; case Teak::AND_imm16_a: EmitConstant(0x82C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS); EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS); @@ -515,6 +518,14 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, llvm_unreachable("Unsupported registers"); break; } + case Teak::SWAP_ab: + { + unsigned aReg = MI.getOperand(2).getReg(); + unsigned bReg = MI.getOperand(3).getReg(); + unsigned swapOp = (encodeAxOp(aReg) << 1) | encodeBxOp(bReg); + EmitConstant(0x4980 | swapOp, 2, OS); + break; + } case Teak::PUSH_regnob16: { unsigned reg = MI.getOperand(0).getReg(); diff --git a/llvm/lib/Target/Teak/TeakISelLowering.cpp b/llvm/lib/Target/Teak/TeakISelLowering.cpp index c2b187d3a90..4bb6e3d6c0b 100644 --- a/llvm/lib/Target/Teak/TeakISelLowering.cpp +++ b/llvm/lib/Target/Teak/TeakISelLowering.cpp @@ -99,6 +99,8 @@ TeakTargetLowering::TeakTargetLowering(const TeakTargetMachine &TeakTM) setOperationAction(ISD::OR, MVT::i16, Custom); setOperationAction(ISD::SUB, MVT::i16, Custom); setOperationAction(ISD::SHL, MVT::i16, Custom); + setOperationAction(ISD::SRL, MVT::i16, Custom); + setOperationAction(ISD::SRA, MVT::i16, Custom); setStackPointerRegisterToSaveRestore(Teak::SP); @@ -342,11 +344,14 @@ SDValue TeakTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, NewWOp);//NewRes); } case ISD::SHL: + case ISD::SRL: + case ISD::SRA: { + DAG.dump(); const SDNode *N = Op.getNode(); SDLoc dl(N); assert(N->getValueType(0) == MVT::i16 && "Unexpected custom legalisation"); - SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i40, N->getOperand(0)); + SDValue NewOp0 = DAG.getNode(Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, MVT::i40, N->getOperand(0)); SDValue NewWOp = DAG.getNode(N->getOpcode(), dl, MVT::i40, NewOp0, N->getOperand(1)); //SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i40, NewWOp, DAG.getValueType(MVT::i16)); return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, NewWOp);//NewRes); diff --git a/llvm/lib/Target/Teak/TeakInstrInfo.cpp b/llvm/lib/Target/Teak/TeakInstrInfo.cpp index 7c449392c6b..c2ab8de6ded 100644 --- a/llvm/lib/Target/Teak/TeakInstrInfo.cpp +++ b/llvm/lib/Target/Teak/TeakInstrInfo.cpp @@ -248,12 +248,15 @@ void TeakInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, dbgs() << "storeRegToStackSlot\n"; dbgs() << "SrcReg: " << SrcReg << "\n"; dbgs() << "TargetRegisterClass: " << RC->getID() << "\n"; + DebugLoc DL; + if (I != MBB.end()) + DL = I->getDebugLoc(); if(RC->hasSuperClassEq(&Teak::ABRegsRegClass)) - BuildMI(MBB, I, I->getDebugLoc(), get(Teak::STORE_REG_TO_STACK_PSEUDO_32)) + BuildMI(MBB, I, DL, get(Teak::STORE_REG_TO_STACK_PSEUDO_32)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex).addImm(0); else - BuildMI(MBB, I, I->getDebugLoc(), get(Teak::STORE_REG_TO_STACK_PSEUDO_16)) + BuildMI(MBB, I, DL, get(Teak::STORE_REG_TO_STACK_PSEUDO_16)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex).addImm(0); @@ -299,11 +302,14 @@ void TeakInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) + DL = I->getDebugLoc(); if(RC->hasSuperClassEq(&Teak::ABRegsRegClass)) - BuildMI(MBB, I, I->getDebugLoc(), get(Teak::LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40), DestReg) + BuildMI(MBB, I, DL, get(Teak::LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40), DestReg) .addFrameIndex(FrameIndex).addImm(0); else - BuildMI(MBB, I, I->getDebugLoc(), get(Teak::LOAD_REG_FROM_STACK_PSEUDO_16), DestReg) + BuildMI(MBB, I, DL, get(Teak::LOAD_REG_FROM_STACK_PSEUDO_16), DestReg) .addFrameIndex(FrameIndex).addImm(0); //dbgs() << "DestReg: " << DestReg << "\n";