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[llvm-exegesis][NFC] Simplify code.

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Summary:
What we're redoing already exists in the X86 backend, it's called
`X86II::getOperandBias`.

Reviewers: gchatelet

Subscribers: tschuett, mstojanovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73340
This commit is contained in:
Clement Courbet 2020-01-24 11:42:27 +01:00
parent ba545c814b
commit 2ee218f365
1 changed files with 1 additions and 6 deletions
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7
llvm/tools/llvm-exegesis/lib/X86/Target.cpp
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@ -673,12 +673,7 @@ void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags); int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags);
assert(MemOpIdx >= 0 && "invalid memory operand index"); assert(MemOpIdx >= 0 && "invalid memory operand index");
// getMemoryOperandNo() ignores tied operands, so we have to add them back. // getMemoryOperandNo() ignores tied operands, so we have to add them back.
for (unsigned I = 0; I <= static_cast<unsigned>(MemOpIdx); ++I) { MemOpIdx += X86II::getOperandBias(IT.getInstr().Description);
const auto &Op = IT.getInstr().Operands[I];
if (Op.isTied() && Op.getTiedToIndex() < I) {
++MemOpIdx;
}
}
setMemOp(IT, MemOpIdx + 0, MCOperand::createReg(Reg)); // BaseReg setMemOp(IT, MemOpIdx + 0, MCOperand::createReg(Reg)); // BaseReg
setMemOp(IT, MemOpIdx + 1, MCOperand::createImm(1)); // ScaleAmt setMemOp(IT, MemOpIdx + 1, MCOperand::createImm(1)); // ScaleAmt
setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(0)); // IndexReg setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(0)); // IndexReg