mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-19 03:25:54 -04:00
Added support for r6, imm8u and memimm16, various fixes
This commit is contained in:
Gericom
parent
f229bdcee8
commit
20cf950cae
@ -313,7 +313,7 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
//if (Desc.getSize() != 4) {
|
||||
// llvm_unreachable("Unexpected instruction size!");
|
||||
//}
|
||||
//dbgs() << "op: " << MI.getOpcode() << "\n";
|
||||
dbgs() << "op: " << MI.getOpcode() << "\n";
|
||||
switch(MI.getOpcode())
|
||||
{
|
||||
case Teak::ADD_ab_ab:
|
||||
@ -331,14 +331,45 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
break;
|
||||
}
|
||||
case Teak::ADD_regnobp016_a:
|
||||
EmitConstant(0x86A0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0xD38B | (encodeAxOp(MI.getOperand(0).getReg()) << 4), 2, OS);
|
||||
else
|
||||
EmitConstant(0x86A0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::ADDL_regnob16_a:
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0x9466 | encodeAxOp(MI.getOperand(0).getReg()), 2, OS);
|
||||
else
|
||||
EmitConstant(0x94A0 | encodeRegisterOp(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::ADD_imm8u_a:
|
||||
EmitConstant(0xC600 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | (MI.getOperand(1).getImm() & 0xFF), 2, OS);
|
||||
break;
|
||||
case Teak::ADD_imm16_a:
|
||||
EmitConstant(0x86C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::ADD_memimm16_a:
|
||||
EmitConstant(0xD4FB | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(1).isImm())
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
else
|
||||
{
|
||||
EmitConstant(0, 2, OS);
|
||||
Fixups.push_back(MCFixup::create(0, MI.getOperand(1).getExpr(), MCFixupKind(Teak::fixup_teak_ptr_imm16)));
|
||||
}
|
||||
break;
|
||||
case Teak::ADD_memrn_a:
|
||||
EmitConstant(0x8680 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::ADDL_memrn_a:
|
||||
EmitConstant(0x9480 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::ADDV_imm16_RegNoBRegs16:
|
||||
EmitConstant(0x87E0 | encodeRegisterOp(MI.getOperand(0).getReg()), 2, OS);
|
||||
if(MI.getOperand(0).getReg() == Teak::R6)
|
||||
EmitConstant(0x47BB, 2, OS);
|
||||
else
|
||||
EmitConstant(0x87E0 | encodeRegisterOp(MI.getOperand(0).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::ADDV_imm16_memrn:
|
||||
@ -351,10 +382,26 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
| (encodeAbOp(MI.getOperand(2).getReg()) << 0)
|
||||
| (encodeAxOp(MI.getOperand(0).getReg()) << 12), 2, OS);
|
||||
break;
|
||||
// case Teak::AND_imm8_a:
|
||||
// EmitConstant(0xC200 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | (MI.getOperand(1).getImm() & 0xFF), 2, OS);
|
||||
// break;
|
||||
case Teak::AND_imm16_a:
|
||||
EmitConstant(0x82C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::AND_memimm16_a:
|
||||
EmitConstant(0xD4F9 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(1).isImm())
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
else
|
||||
{
|
||||
EmitConstant(0, 2, OS);
|
||||
Fixups.push_back(MCFixup::create(0, MI.getOperand(1).getExpr(), MCFixupKind(Teak::fixup_teak_ptr_imm16)));
|
||||
}
|
||||
break;
|
||||
case Teak::AND_memrn_a:
|
||||
EmitConstant(0x8280 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::BR_imm18:
|
||||
case Teak::BRCond_imm18:
|
||||
{
|
||||
@ -390,23 +437,47 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
break;
|
||||
}
|
||||
case Teak::CMP_regnobp016_a:
|
||||
EmitConstant(0x8CA0 | encodeRegisterP0Op(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(0).getReg() == Teak::R6)
|
||||
EmitConstant(0xD38E | (encodeAxOp(MI.getOperand(1).getReg()) << 4), 2, OS);
|
||||
else
|
||||
EmitConstant(0x8CA0 | encodeRegisterP0Op(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::CMPU_regnob016_a:
|
||||
EmitConstant(0x9EA0 | encodeRegisterOp(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(0).getReg() == Teak::R6)
|
||||
EmitConstant(0x8A63 | (encodeAxOp(MI.getOperand(1).getReg()) << 3), 2, OS);
|
||||
else
|
||||
EmitConstant(0x9EA0 | encodeRegisterOp(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::CMP_imm8u_a:
|
||||
EmitConstant(0xCC00 | (encodeAxOp(MI.getOperand(1).getReg()) << 8) | (MI.getOperand(0).getImm() & 0xFF), 2, OS);
|
||||
break;
|
||||
case Teak::CMP_imm16_a:
|
||||
{
|
||||
EmitConstant(0x8CC0 | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
}
|
||||
case Teak::CMPV_imm16_RegNoBRegs16:
|
||||
{
|
||||
EmitConstant(0x8DE0 | encodeRegisterOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0x47BE, 2, OS);
|
||||
else
|
||||
EmitConstant(0x8DE0 | encodeRegisterOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
}
|
||||
case Teak::CMP_memimm16_a:
|
||||
EmitConstant(0xD4FE | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
if(MI.getOperand(1).isImm())
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
else
|
||||
{
|
||||
EmitConstant(0, 2, OS);
|
||||
Fixups.push_back(MCFixup::create(0, MI.getOperand(1).getExpr(), MCFixupKind(Teak::fixup_teak_ptr_imm16)));
|
||||
}
|
||||
break;
|
||||
case Teak::CMP_memrn_a:
|
||||
EmitConstant(0x8C80 | encodeRnOp(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::CMPU_memrn_a:
|
||||
EmitConstant(0x9E80 | encodeRnOp(MI.getOperand(0).getReg()) | (encodeAxOp(MI.getOperand(1).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::MOV_imm16_regnob16:
|
||||
case Teak::MOV_imm16neg_ab:
|
||||
case Teak::MOV_imm16_ab:
|
||||
@ -417,7 +488,9 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
reg = teakGetAbLReg(reg);
|
||||
else if(MI.getOpcode() == Teak::MOV_imm16hi_ab)
|
||||
reg = teakGetAbHReg(reg);
|
||||
if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg) || TeakMCRegisterClasses[Teak::RegNoBRegs40RegClassID].contains(reg))
|
||||
if(reg == Teak::R6)
|
||||
EmitConstant(0x0023, 2, OS);
|
||||
else if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg) || TeakMCRegisterClasses[Teak::RegNoBRegs40RegClassID].contains(reg))
|
||||
EmitConstant(0x5E00 | encodeRegisterOp(reg), 2, OS);
|
||||
else
|
||||
EmitConstant(0x5E20 | (encodeBxOp(reg) << 8), 2, OS);
|
||||
@ -442,10 +515,22 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
unsigned dstReg = MI.getOperand(0).getReg();
|
||||
if(MI.getOpcode() == Teak::MOV_regnobp016_abl)
|
||||
dstReg = teakGetAbLReg(dstReg);
|
||||
if(TeakMCRegisterClasses[Teak::BRegsRegClassID].contains(dstReg))
|
||||
EmitConstant(0x5EC0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeBxOp(dstReg) << 5), 2, OS);
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
{
|
||||
if(TeakMCRegisterClasses[Teak::BRegsRegClassID].contains(dstReg))
|
||||
EmitConstant(0xD481 | (encodeBxOp(dstReg) << 8), 2, OS);
|
||||
else
|
||||
EmitConstant(0x5F00 | encodeRegisterOp(dstReg), 2, OS);
|
||||
}
|
||||
else if(dstReg == Teak::R6)
|
||||
EmitConstant(0x5F60 | encodeRegisterOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
else
|
||||
EmitConstant(0x5800 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeRegisterOp(dstReg) << 5), 2, OS);
|
||||
{
|
||||
if(TeakMCRegisterClasses[Teak::BRegsRegClassID].contains(dstReg))
|
||||
EmitConstant(0x5EC0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeBxOp(dstReg) << 5), 2, OS);
|
||||
else
|
||||
EmitConstant(0x5800 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeRegisterOp(dstReg) << 5), 2, OS);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case Teak::MOV_regnob16_memrn:
|
||||
@ -454,7 +539,10 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
unsigned reg = MI.getOperand(0).getReg();
|
||||
if(MI.getOpcode() == Teak::MOV_abl_memrn)
|
||||
reg = teakGetAbLReg(reg);
|
||||
EmitConstant(0x1800 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeRegisterOp(reg) << 5), 2, OS);
|
||||
if(reg == Teak::R6)
|
||||
EmitConstant(0x1B00 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
else
|
||||
EmitConstant(0x1800 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeRegisterOp(reg) << 5), 2, OS);
|
||||
break;
|
||||
}
|
||||
case Teak::MOV_memimm16_a:
|
||||
@ -476,7 +564,12 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
unsigned dstReg = MI.getOperand(0).getReg();
|
||||
if(MI.getOpcode() == Teak::MOV_memrn_ab1)
|
||||
dstReg = teakGetAbLReg(dstReg);
|
||||
EmitConstant(0x1C00 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeRegisterOp(dstReg) << 5), 2, OS);
|
||||
if(dstReg == Teak::R6)
|
||||
EmitConstant(0x1B20 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
else if(TeakMCRegisterClasses[Teak::BRegsRegClassID].contains(dstReg))
|
||||
EmitConstant(0x98C0 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeBxOp(dstReg) << 8), 2, OS);
|
||||
else
|
||||
EmitConstant(0x1C00 | encodeRnOp(MI.getOperand(1).getReg()) | (encodeRegisterOp(dstReg) << 5), 2, OS);
|
||||
break;
|
||||
}
|
||||
case Teak::MOV_r7offset16_a:
|
||||
@ -502,7 +595,10 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
break;
|
||||
}
|
||||
case Teak::MPY_y0_regnob16:
|
||||
EmitConstant(0x8040 | encodeRegisterOp(MI.getOperand(2).getReg()), 2, OS);
|
||||
if(MI.getOperand(2).getReg() == Teak::R6)
|
||||
EmitConstant(0x5EA0, 2, OS);
|
||||
else
|
||||
EmitConstant(0x8040 | encodeRegisterOp(MI.getOperand(2).getReg()), 2, OS);
|
||||
break;
|
||||
case Teak::NEG_a:
|
||||
EmitConstant(0x6790 | (encodeAxOp(MI.getOperand(0).getReg()) << 12), 2, OS);
|
||||
@ -527,6 +623,9 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
llvm_unreachable("Unsupported registers");
|
||||
break;
|
||||
}
|
||||
case Teak::OR_imm8u_a:
|
||||
EmitConstant(0xC000 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | (MI.getOperand(1).getImm() & 0xFF), 2, OS);
|
||||
break;
|
||||
case Teak::OR_imm16_a:
|
||||
EmitConstant(0x80C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
@ -542,7 +641,10 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
unsigned aReg = MI.getOperand(0).getReg();
|
||||
if(MI.getOpcode() == Teak::RST_imm16_abl)
|
||||
aReg = teakGetAbLReg(aReg);
|
||||
EmitConstant(0x83E0 | encodeRegisterOp(aReg), 2, OS);
|
||||
if(aReg == Teak::R6)
|
||||
EmitConstant(0x47B9, 2, OS);
|
||||
else
|
||||
EmitConstant(0x83E0 | encodeRegisterOp(aReg), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
}
|
||||
@ -553,13 +655,21 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
break;
|
||||
}
|
||||
|
||||
case Teak::RST_imm16_memrn:
|
||||
EmitConstant(0x82E0 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
|
||||
case Teak::SET_imm16_regnob16:
|
||||
case Teak::SET_imm16_abl:
|
||||
{
|
||||
unsigned aReg = MI.getOperand(0).getReg();
|
||||
if(MI.getOpcode() == Teak::SET_imm16_abl)
|
||||
aReg = teakGetAbLReg(aReg);
|
||||
EmitConstant(0x81E0 | encodeRegisterOp(aReg), 2, OS);
|
||||
if(aReg == Teak::R6)
|
||||
EmitConstant(0x47B8, 2, OS);
|
||||
else
|
||||
EmitConstant(0x81E0 | encodeRegisterOp(aReg), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
}
|
||||
@ -569,6 +679,11 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
}
|
||||
|
||||
case Teak::SET_imm16_memrn:
|
||||
EmitConstant(0x80E0 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
|
||||
case Teak::SHFC_arith_ab_ab_sv:
|
||||
EmitConstant(0xD280
|
||||
@ -582,6 +697,37 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
| (encodeAbOp(MI.getOperand(0).getReg()) << 7)
|
||||
| (MI.getOperand(2).getImm() & 0x3F), 2, OS);
|
||||
break;
|
||||
|
||||
case Teak::SUB_regnobp016_a:
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0xD38F | (encodeAxOp(MI.getOperand(0).getReg()) << 4), 2, OS);
|
||||
else
|
||||
EmitConstant(0x8EA0 | encodeRegisterP0Op(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::SUBL_regnob16_a:
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0x5E22 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
else
|
||||
EmitConstant(0x98A0 | encodeRegisterOp(MI.getOperand(1).getReg()) | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
break;
|
||||
case Teak::SUB_imm8u_a:
|
||||
EmitConstant(0xCE00 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | (MI.getOperand(1).getImm() & 0xFF), 2, OS);
|
||||
break;
|
||||
case Teak::SUB_imm16_a:
|
||||
EmitConstant(0x8EC0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::SUBV_imm16_RegNoBRegs16:
|
||||
if(MI.getOperand(0).getReg() == Teak::R6)
|
||||
EmitConstant(0x47BF, 2, OS);
|
||||
else
|
||||
EmitConstant(0x8FE0 | encodeRegisterOp(MI.getOperand(0).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::SUBV_imm16_memrn:
|
||||
EmitConstant(0x8EE0 | encodeRnOp(MI.getOperand(1).getReg()), 2, OS);
|
||||
EmitConstant(MI.getOperand(0).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
|
||||
case Teak::SUB_ab_ab:
|
||||
{
|
||||
@ -608,7 +754,9 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
case Teak::PUSH_regnob16:
|
||||
{
|
||||
unsigned reg = MI.getOperand(0).getReg();
|
||||
if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg))
|
||||
if(reg == Teak::R6)
|
||||
EmitConstant(0xD4D7, 2, OS);
|
||||
else if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg))
|
||||
EmitConstant(0x5E40 | encodeRegisterOp(reg), 2, OS);
|
||||
else
|
||||
llvm_unreachable("Unsupported register");
|
||||
@ -620,7 +768,9 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
case Teak::POP_regnob16:
|
||||
{
|
||||
unsigned reg = MI.getOperand(0).getReg();
|
||||
if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg))
|
||||
if(reg == Teak::R6)
|
||||
EmitConstant(0x0024, 2, OS);
|
||||
else if(TeakMCRegisterClasses[Teak::RegNoBRegs16RegClassID].contains(reg))
|
||||
EmitConstant(0x5E60 | encodeRegisterOp(reg), 2, OS);
|
||||
else
|
||||
llvm_unreachable("Unsupported register");
|
||||
@ -639,13 +789,19 @@ void TeakMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
EmitConstant(MI.getOperand(0).getImm(), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm(), 2, OS);
|
||||
break;
|
||||
case Teak::XOR_imm16_a:
|
||||
case Teak::XOR_imm8u_a:
|
||||
EmitConstant(0xC400 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | (MI.getOperand(1).getImm() & 0xFF), 2, OS);
|
||||
break;
|
||||
case Teak::XOR_imm16_a:
|
||||
EmitConstant(0x84C0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8), 2, OS);
|
||||
EmitConstant(MI.getOperand(1).getImm() & 0xFFFF, 2, OS);
|
||||
break;
|
||||
case Teak::XOR_regnobp016_a:
|
||||
case Teak::XOR_a_a:
|
||||
EmitConstant(0x84A0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | encodeRegisterP0Op(MI.getOperand(1).getReg()), 2, OS);
|
||||
if(MI.getOperand(1).getReg() == Teak::R6)
|
||||
EmitConstant(0xD38A | (encodeAxOp(MI.getOperand(0).getReg()) << 4), 2, OS);
|
||||
else
|
||||
EmitConstant(0x84A0 | (encodeAxOp(MI.getOperand(0).getReg()) << 8) | encodeRegisterP0Op(MI.getOperand(1).getReg()), 2, OS);
|
||||
break;
|
||||
default:
|
||||
dbgs() << "Unsupported opcode " << MI.getOpcode() << "!\n";
|
||||
|
||||
@ -29,6 +29,20 @@ def Imm6s : Operand<i16>, ImmLeaf<i16, [{
|
||||
let ParserMatchClass = Imm6sAsmOperand;
|
||||
}
|
||||
|
||||
def Imm8uAsmOperand: ImmAsmOperand<0,255> { let Name = "Imm8u"; }
|
||||
def Imm8u : Operand<i40>, ImmLeaf<i40, [{
|
||||
return Imm >= 0 && Imm <= 255;
|
||||
}]> {
|
||||
let ParserMatchClass = Imm8uAsmOperand;
|
||||
}
|
||||
|
||||
def Imm8u_16AsmOperand: ImmAsmOperand<0,255> { let Name = "Imm8u_16"; }
|
||||
def Imm8u_16 : Operand<i16>, ImmLeaf<i16, [{
|
||||
return Imm >= 0 && Imm <= 255;
|
||||
}]> {
|
||||
let ParserMatchClass = Imm8u_16AsmOperand;
|
||||
}
|
||||
|
||||
def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; }
|
||||
def imm0_65535 : Operand<i40>, ImmLeaf<i40, [{
|
||||
return Imm >= 0 && Imm < 65536;
|
||||
@ -69,341 +83,140 @@ def imm0_262143 : Operand<i32>, ImmLeaf<i32, [{
|
||||
// def : Pat<(sext_inreg i16:$src, i8),
|
||||
// (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>;
|
||||
|
||||
let Defs = [ICC], isCommutable = 1 in
|
||||
def ADDV_imm16_memrn : InstTeakImm16<
|
||||
(outs ),
|
||||
(ins immNeg32768_32767_16:$val, GRRegs:$addr),
|
||||
"addv $val, [$addr]",
|
||||
[(store (add (load GRRegs:$addr), immNeg32768_32767_16:$val), GRRegs:$addr)]>;
|
||||
// let Defs = [ICC], isCommutable = 1 in
|
||||
// def ADDV_imm16_memrn : InstTeakImm16<
|
||||
// (outs ),
|
||||
// (ins immNeg32768_32767_16:$val, GRRegs:$addr),
|
||||
// "addv $val, [$addr]",
|
||||
// [(store (add (load GRRegs:$addr), immNeg32768_32767_16:$val), GRRegs:$addr)]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADDV_imm16_RegNoBRegs16 : InstTeakImm16<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins immNeg32768_32767_16:$val, RegNoBRegs16:$a),
|
||||
"addv $val, $a",
|
||||
[(set RegNoBRegs16:$dst, (add RegNoBRegs16:$a, immNeg32768_32767_16:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADD_imm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins immNeg32768_32767:$val, ARegs:$a),
|
||||
"add $val, $a",
|
||||
[(set ARegs:$dst, (add ARegs:$a, immNeg32768_32767:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def ADD_regnobp016_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins RegNoBRegs16:$nob, ARegs:$a),
|
||||
"add $nob, $a",
|
||||
[(set ARegs:$dst, (add ARegs:$a, (sext RegNoBRegs16:$nob)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADD_ab_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$b, ABRegs:$a),
|
||||
"add $b, $a",
|
||||
[(set ABRegs:$dst, (add ABRegs:$a, ABRegs:$b))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def AND_imm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins imm0_65535:$val, ARegs:$a),
|
||||
"and $val, $a",
|
||||
[(set ARegs:$dst, (and ARegs:$a, imm0_65535:$val))]>;
|
||||
|
||||
let Defs = [ICC] in
|
||||
def AND_ab_ab_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins ABRegs:$b, ABRegs:$a),
|
||||
"and $b, $a, $dst",
|
||||
[(set ARegs:$dst, (and ABRegs:$a, ABRegs:$b))]>;
|
||||
{
|
||||
let isCommutable = 1, mayStore = 1, mayLoad = 1 in
|
||||
def ADDV_imm16_memrn : InstTeakImm16<(outs), (ins immNeg32768_32767:$val, GRRegs:$addr), "addv $val, [$addr]", [(truncstorei16 (add (extloadi16 GRRegs:$addr), immNeg32768_32767:$val), GRRegs:$addr)]>;
|
||||
|
||||
let Defs = [ICC] in
|
||||
def OR_ab_ab_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins ABRegs:$b, ABRegs:$a),
|
||||
"or $b, $a, $dst",
|
||||
[(set ARegs:$dst, (or ABRegs:$a, ABRegs:$b))]>;
|
||||
let mayStore = 1, mayLoad = 1 in
|
||||
def SUBV_imm16_memrn : InstTeakImm16<(outs), (ins immNeg32768_32767:$val, GRRegs:$addr), "subv $val, [$addr]", [(truncstorei16 (sub (extloadi16 GRRegs:$addr), immNeg32768_32767:$val), GRRegs:$addr)]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def OR_imm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins imm0_65535:$val, ARegs:$a),
|
||||
"or $val, $a",
|
||||
[(set ARegs:$dst, (or ARegs:$a, imm0_65535:$val))]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADDV_imm16_RegNoBRegs16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins immNeg32768_32767:$val, RegNoBRegs16:$a), "addv $val, $a", [(set RegNoBRegs16:$dst, (trunc (add (anyext RegNoBRegs16:$a), immNeg32768_32767:$val)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def RST_imm16_regnob16 : InstTeakImm16<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins imm0_65535_16:$val, RegNoBRegs16:$a),
|
||||
"rst $val, $a",
|
||||
[(set RegNoBRegs16:$dst, (and RegNoBRegs16:$a, (not imm0_65535_16:$val)))]>;
|
||||
let Constraints = "$dst = $a" in
|
||||
def SUBV_imm16_RegNoBRegs16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins immNeg32768_32767:$val, RegNoBRegs16:$a), "subv $val, $a", [(set RegNoBRegs16:$dst, (trunc (sub (anyext RegNoBRegs16:$a), immNeg32768_32767:$val)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def RST_imm16_abl : InstTeakImm16<
|
||||
(outs ABRegs:$dst),
|
||||
(ins imm0_65535:$val, ABRegs:$a),
|
||||
"rst $val, ${a}l",
|
||||
[(set ABRegs:$dst, (and ABRegs:$a, (not imm0_65535:$val)))]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADD_imm8u_a : InstTeak<(outs ARegs:$dst), (ins Imm8u:$val, ARegs:$a), "add ${val}u8, $a", [(set ARegs:$dst, (add ARegs:$a, Imm8u:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def RST_imm16_sttmod : InstTeakImm16<
|
||||
(outs SttModRegs:$dst),
|
||||
(ins imm0_65535_16:$val, SttModRegs:$a),
|
||||
"rst $val, $a",
|
||||
[]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADD_imm16_a : InstTeakImm16<(outs ARegs:$dst), (ins immNeg32768_32767:$val, ARegs:$a), "add $val, $a", [(set ARegs:$dst, (add ARegs:$a, immNeg32768_32767:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SET_imm16_regnob16 : InstTeakImm16<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins imm0_65535_16:$val, RegNoBRegs16:$a),
|
||||
"set $val, $a",
|
||||
[(set RegNoBRegs16:$dst, (or RegNoBRegs16:$a, imm0_65535_16:$val))]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1, mayLoad = 1 in
|
||||
def ADD_memimm16_a : InstTeakImm16<(outs ARegs:$dst), (ins Operand<i16>:$addr, ARegs:$a), "add [$addr], $a", [(set ARegs:$dst, (add ARegs:$a, (sextloadi16 imm:$addr)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SET_imm16_abl : InstTeakImm16<
|
||||
(outs ABRegs:$dst),
|
||||
(ins imm0_65535:$val, ABRegs:$a),
|
||||
"set $val, ${a}l",
|
||||
[(set ABRegs:$dst, (or ABRegs:$a, imm0_65535:$val))]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1, mayLoad = 1 in
|
||||
def ADD_memrn_a : InstTeak<(outs ARegs:$dst), (ins GRRegs:$addr, ARegs:$a), "add [$addr], $a", [(set ARegs:$dst, (add ARegs:$a, (sextloadi16 GRRegs:$addr)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SET_imm16_sttmod : InstTeakImm16<
|
||||
(outs SttModRegs:$dst),
|
||||
(ins imm0_65535_16:$val, SttModRegs:$a),
|
||||
"set $val, $a",
|
||||
[]>;
|
||||
let Constraints = "$dst = $a", mayLoad = 1 in
|
||||
def ADDL_memrn_a : InstTeak<(outs ARegs:$dst), (ins GRRegs:$addr, ARegs:$a), "addl [$addr], $a", [(set ARegs:$dst, (add ARegs:$a, (zextloadi16 GRRegs:$addr)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def OR_r7offset16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins memsrc:$offset, ARegs:$a),
|
||||
"or $offset, $a",
|
||||
[]>;
|
||||
let Constraints = "$dst = $a" in
|
||||
def ADD_regnobp016_a : InstTeak<(outs ARegs:$dst), (ins RegNoBRegs16:$nob, ARegs:$a), "add $nob, $a", [(set ARegs:$dst, (add ARegs:$a, (sext RegNoBRegs16:$nob)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SUB_regnobp016_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins RegNoBRegs16:$nob, ARegs:$a),
|
||||
"sub $nob, $a",
|
||||
[(set ARegs:$dst, (sub ARegs:$a, (sext RegNoBRegs16:$nob)))]>;
|
||||
let Constraints = "$dst = $a" in
|
||||
def ADDL_regnob16_a : InstTeak<(outs ARegs:$dst), (ins RegNoBRegs16:$nob, ARegs:$a), "addl $nob, $a", [(set ARegs:$dst, (add ARegs:$a, (zext RegNoBRegs16:$nob)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SUB_ab_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$b, ABRegs:$a),
|
||||
"sub $b, $a",
|
||||
[(set ABRegs:$dst, (sub ABRegs:$a, ABRegs:$b))]>;
|
||||
let Constraints = "$dst = $a", isCommutable = 1 in
|
||||
def ADD_ab_ab : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$b, ABRegs:$a), "add $b, $a", [(set ABRegs:$dst, (add ABRegs:$a, ABRegs:$b))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SUB_imm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins immNeg32768_32767:$val, ARegs:$a),
|
||||
"sub $val, $a",
|
||||
[(set ARegs:$dst, (sub ARegs:$a, immNeg32768_32767:$val))]>;
|
||||
//this does not give the expected result, it is actually
|
||||
//a = a & (0xFF00 | val)
|
||||
// let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
// def AND_imm8_a : InstTeak<
|
||||
// (outs ARegs:$dst),
|
||||
// (ins Imm8u:$val, ARegs:$a),
|
||||
// "and $val, $a",
|
||||
// [(set ARegs:$dst, (and ARegs:$a, Imm8u:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def SUBV_imm16_RegNoBRegs16 : InstTeakImm16<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins immNeg32768_32767_16:$val, RegNoBRegs16:$a),
|
||||
"subv $val, $a",
|
||||
[(set RegNoBRegs16:$dst, (sub RegNoBRegs16:$a, immNeg32768_32767_16:$val))]>;
|
||||
let mayStore = 1, mayLoad = 1 in
|
||||
def RST_imm16_memrn : InstTeakImm16<(outs), (ins imm0_65535_16:$val, GRRegs:$addr), "rst $val, [$addr]", [(truncstorei16 (and (extloadi16 GRRegs:$addr), (not imm0_65535_16:$val)), GRRegs:$addr)]>;
|
||||
|
||||
let Defs = [ICC], isMoveImm = 1 in
|
||||
def MOV_imm16_regnob16 : InstTeakImm16<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins i16imm:$val),
|
||||
"mov $val, $dst",
|
||||
[(set RegNoBRegs16:$dst, imm:$val)]>;
|
||||
let mayStore = 1, mayLoad = 1 in
|
||||
def SET_imm16_memrn : InstTeakImm16<(outs), (ins imm0_65535_16:$val, GRRegs:$addr), "set $val, [$addr]", [(truncstorei16 (or (extloadi16 GRRegs:$addr), imm0_65535_16:$val), GRRegs:$addr)]>;
|
||||
|
||||
let Defs = [ICC], isMoveImm = 1 in
|
||||
def MOV_imm16neg_ab : InstTeakImm16<
|
||||
(outs ABRegs:$dst),
|
||||
(ins immNeg32768_32767:$val),
|
||||
"mov $val, $dst",
|
||||
[(set ABRegs:$dst, immNeg32768_32767:$val)]>;
|
||||
let Constraints = "$dst = $a" in
|
||||
{
|
||||
def AND_imm16_a : InstTeakImm16<(outs ARegs:$dst), (ins imm0_65535:$val, ARegs:$a), "and $val, $a", [(set ARegs:$dst, (and ARegs:$a, imm0_65535:$val))]>;
|
||||
|
||||
let Defs = [ICC], isMoveImm = 1 in
|
||||
def MOV_imm16_ab : InstTeakImm16<
|
||||
(outs ABRegs:$dst),
|
||||
(ins imm0_65535:$val),
|
||||
"mov $val, ${dst}l",
|
||||
[(set ABRegs:$dst, imm0_65535:$val)]>;
|
||||
let mayLoad = 1 in
|
||||
{
|
||||
def AND_memimm16_a : InstTeakImm16<(outs ARegs:$dst), (ins Operand<i16>:$addr, ARegs:$a), "and [$addr], $a", [(set ARegs:$dst, (and ARegs:$a, (zextloadi16 imm:$addr)))]>;
|
||||
def AND_memrn_a : InstTeak<(outs ARegs:$dst), (ins GRRegs:$addr, ARegs:$a), "and [$addr], $a", [(set ARegs:$dst, (and ARegs:$a, (zextloadi16 GRRegs:$addr)))]>;
|
||||
}
|
||||
|
||||
let Defs = [ICC], isMoveImm = 1 in
|
||||
def MOV_imm16hi_ab : InstTeakImm16<
|
||||
(outs ABRegs:$dst),
|
||||
(ins imm0_65535:$val),
|
||||
"mov $val, ${dst}h",
|
||||
[]>;
|
||||
def OR_imm8u_a : InstTeakImm16<(outs ARegs:$dst), (ins Imm8u:$val, ARegs:$a), "or ${val}u8, $a", [(set ARegs:$dst, (or ARegs:$a, Imm8u:$val))]>;
|
||||
def OR_imm16_a : InstTeakImm16<(outs ARegs:$dst), (ins imm0_65535:$val, ARegs:$a), "or $val, $a", [(set ARegs:$dst, (or ARegs:$a, imm0_65535:$val))]>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_ab_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$src),
|
||||
"mov $src, $dst",
|
||||
[/*(set ABRegs:$dst, ABRegs:$src)*/]>;
|
||||
def RST_imm16_regnob16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins imm0_65535_16:$val, RegNoBRegs16:$a), "rst $val, $a", [(set RegNoBRegs16:$dst, (and RegNoBRegs16:$a, (not imm0_65535_16:$val)))]>;
|
||||
def RST_imm16_abl : InstTeakImm16<(outs ABRegs:$dst), (ins imm0_65535:$val, ABRegs:$a), "rst $val, ${a}l", [(set ABRegs:$dst, (and ABRegs:$a, (not imm0_65535:$val)))]>;
|
||||
def RST_imm16_sttmod : InstTeakImm16<(outs SttModRegs:$dst), (ins imm0_65535_16:$val, SttModRegs:$a), "rst $val, $a", []>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_regnobp016_regnob16 : InstTeak<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins RegNoBRegs16:$src),
|
||||
"mov $src, $dst",
|
||||
[/*(set RegNoBRegs16:$dst, RegNoBRegs16:$src)*/]>;
|
||||
def SET_imm16_regnob16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins imm0_65535_16:$val, RegNoBRegs16:$a), "set $val, $a", [(set RegNoBRegs16:$dst, (or RegNoBRegs16:$a, imm0_65535_16:$val))]>;
|
||||
def SET_imm16_abl : InstTeakImm16<(outs ABRegs:$dst), (ins imm0_65535:$val, ABRegs:$a), "set $val, ${a}l", [(set ABRegs:$dst, (or ABRegs:$a, imm0_65535:$val))]>;
|
||||
def SET_imm16_sttmod : InstTeakImm16<(outs SttModRegs:$dst), (ins imm0_65535_16:$val, SttModRegs:$a), "set $val, $a", []>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_p0_regnob16 : InstTeak<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins P0Regs:$src),
|
||||
"mov $src, $dst",
|
||||
[/*(set RegNoBRegs16:$dst, RegNoBRegs16:$src)*/]>;
|
||||
def OR_r7offset16_a : InstTeakImm16<(outs ARegs:$dst), (ins memsrc:$offset, ARegs:$a), "or $offset, $a", []>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_regnobp016_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins RegNoBRegs16:$src),
|
||||
"mov $src, $dst",
|
||||
[(set ABRegs:$dst, (sext RegNoBRegs16:$src))]>;
|
||||
//def SUBV_imm16_RegNoBRegs16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins immNeg32768_32767_16:$val, RegNoBRegs16:$a), "subv $val, $a", [(set RegNoBRegs16:$dst, (sub RegNoBRegs16:$a, immNeg32768_32767_16:$val))]>;
|
||||
def SUB_imm8u_a : InstTeakImm16<(outs ARegs:$dst), (ins Imm8u:$val, ARegs:$a), "sub ${val}u8, $a", [(set ARegs:$dst, (sub ARegs:$a, Imm8u:$val))]>;
|
||||
def SUB_imm16_a : InstTeakImm16<(outs ARegs:$dst), (ins immNeg32768_32767:$val, ARegs:$a), "sub $val, $a", [(set ARegs:$dst, (sub ARegs:$a, immNeg32768_32767:$val))]>;
|
||||
def SUB_regnobp016_a : InstTeak<(outs ARegs:$dst), (ins RegNoBRegs16:$nob, ARegs:$a), "sub $nob, $a", [(set ARegs:$dst, (sub ARegs:$a, (sext RegNoBRegs16:$nob)))]>;
|
||||
def SUBL_regnob16_a : InstTeak<(outs ARegs:$dst), (ins RegNoBRegs16:$nob, ARegs:$a), "subl $nob, $a", [(set ARegs:$dst, (sub ARegs:$a, (zext RegNoBRegs16:$nob)))]>;
|
||||
def SUB_ab_ab : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$b, ABRegs:$a), "sub $b, $a", [(set ABRegs:$dst, (sub ABRegs:$a, ABRegs:$b))]>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_p0_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins P0Regs:$src),
|
||||
"mov $src, $dst",
|
||||
[/*(set ABRegs:$dst, (sext P0Regs:$src))*/]>;
|
||||
def NEG_a : InstTeak<(outs ARegs:$dst), (ins ARegs:$a), "neg $a", [(set ARegs:$dst, (ineg ARegs:$a))]>;
|
||||
def NOT_a : InstTeak<(outs ARegs:$dst), (ins ARegs:$a), "not $a", [(set ARegs:$dst, (not ARegs:$a))]>;
|
||||
|
||||
let Defs = [ICC], isMoveReg = 1 in
|
||||
def MOV_regnobp016_abl : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins RegNoBRegs16:$src),
|
||||
"mov $src, ${dst}l",
|
||||
[(set ABRegs:$dst, (zext RegNoBRegs16:$src))]>;
|
||||
def XOR_imm8u_a : InstTeak<(outs ARegs:$dst), (ins Imm8u:$val, ARegs:$a), "xor ${val}u8, $a", [(set ARegs:$dst, (xor ARegs:$a, Imm8u:$val))]>;
|
||||
def XOR_imm16_a : InstTeakImm16<(outs ARegs:$dst), (ins imm0_65535:$val, ARegs:$a), "xor $val, $a", [(set ARegs:$dst, (xor ARegs:$a, imm0_65535:$val))]>;
|
||||
def XOR_regnobp016_a : InstTeakImm16<(outs ARegs:$dst), (ins RegNoBRegs16:$b, ARegs:$a), "xor $b, $a", [(set ARegs:$dst, (xor ARegs:$a, (zext RegNoBRegs16:$b)))]>;
|
||||
def XOR_a_a : InstTeakImm16<(outs ARegs:$dst), (ins ARegs:$b, ARegs:$a), "xor $b, $a", [(set ARegs:$dst, (xor ARegs:$a, ARegs:$b))]>;
|
||||
}
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def NEG_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins ARegs:$a),
|
||||
"neg $a",
|
||||
[(set ARegs:$dst, (ineg ARegs:$a))]>;
|
||||
def AND_ab_ab_a : InstTeak<(outs ARegs:$dst), (ins ABRegs:$b, ABRegs:$a), "and $b, $a, $dst", [(set ARegs:$dst, (and ABRegs:$a, ABRegs:$b))]>;
|
||||
def OR_ab_ab_a : InstTeak<(outs ARegs:$dst), (ins ABRegs:$b, ABRegs:$a), "or $b, $a, $dst", [(set ARegs:$dst, (or ABRegs:$a, ABRegs:$b))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def NOT_a : InstTeak<
|
||||
(outs ARegs:$dst),
|
||||
(ins ARegs:$a),
|
||||
"not $a",
|
||||
[(set ARegs:$dst, (not ARegs:$a))]>;
|
||||
let isMoveImm = 1 in
|
||||
{
|
||||
def MOV_imm16_regnob16 : InstTeakImm16<(outs RegNoBRegs16:$dst), (ins i16imm:$val), "mov $val, $dst", [(set RegNoBRegs16:$dst, imm:$val)]>;
|
||||
def MOV_imm16neg_ab : InstTeakImm16<(outs ABRegs:$dst), (ins immNeg32768_32767:$val), "mov $val, $dst", [(set ABRegs:$dst, immNeg32768_32767:$val)]>;
|
||||
def MOV_imm16_ab : InstTeakImm16<(outs ABRegs:$dst), (ins imm0_65535:$val), "mov $val, ${dst}l", [(set ABRegs:$dst, imm0_65535:$val)]>;
|
||||
def MOV_imm16hi_ab : InstTeakImm16<(outs ABRegs:$dst), (ins imm0_65535:$val), "mov $val, ${dst}h", []>;
|
||||
}
|
||||
|
||||
let Defs = [ICC] in
|
||||
def SHFI_arith_ab_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$src, Imm6s:$shift),
|
||||
"shfi $src, $dst, $shift",
|
||||
[(set ABRegs:$dst, (TeakShiftArith ABRegs:$src, Imm6s:$shift))]>;
|
||||
let isMoveReg = 1 in
|
||||
{
|
||||
def MOV_ab_ab : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$src), "mov $src, $dst", [/*(set ABRegs:$dst, ABRegs:$src)*/]>;
|
||||
def MOV_regnobp016_regnob16 : InstTeak<(outs RegNoBRegs16:$dst), (ins RegNoBRegs16:$src), "mov $src, $dst", [/*(set RegNoBRegs16:$dst, RegNoBRegs16:$src)*/]>;
|
||||
def MOV_p0_regnob16 : InstTeak<(outs RegNoBRegs16:$dst), (ins P0Regs:$src), "mov $src, $dst", [/*(set RegNoBRegs16:$dst, RegNoBRegs16:$src)*/]>;
|
||||
def MOV_regnobp016_ab : InstTeak<(outs ABRegs:$dst), (ins RegNoBRegs16:$src), "mov $src, $dst", [(set ABRegs:$dst, (sext RegNoBRegs16:$src))]>;
|
||||
def MOV_p0_ab : InstTeak<(outs ABRegs:$dst), (ins P0Regs:$src), "mov $src, $dst", [/*(set ABRegs:$dst, (sext P0Regs:$src))*/]>;
|
||||
def MOV_regnobp016_abl : InstTeak<(outs ABRegs:$dst), (ins RegNoBRegs16:$src), "mov $src, ${dst}l", [(set ABRegs:$dst, (zext RegNoBRegs16:$src))]>;
|
||||
}
|
||||
|
||||
let Defs = [ICC] in
|
||||
def SHFI_logic_ab_ab : TeakPseudoInst<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$src, Imm6s:$shift),
|
||||
"shfi $src, $dst, $shift",
|
||||
[(set ABRegs:$dst, (TeakShiftLogic ABRegs:$src, Imm6s:$shift))]>;
|
||||
def SHFI_arith_ab_ab : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$src, Imm6s:$shift), "shfi $src, $dst, $shift", [(set ABRegs:$dst, (TeakShiftArith ABRegs:$src, Imm6s:$shift))]>;
|
||||
def SHFI_logic_ab_ab : TeakPseudoInst<(outs ABRegs:$dst), (ins ABRegs:$src, Imm6s:$shift), "shfi $src, $dst, $shift", [(set ABRegs:$dst, (TeakShiftLogic ABRegs:$src, Imm6s:$shift))]>;
|
||||
def SHFC_arith_ab_ab_sv : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$src, SVReg:$shift), "shfc $src, $dst, always", [(set ABRegs:$dst, (TeakShiftArith ABRegs:$src, SVReg:$shift))]>;
|
||||
def SHFC_logic_ab_ab_sv : TeakPseudoInst<(outs ABRegs:$dst), (ins ABRegs:$src, SVReg:$shift), "shfc $src, $dst, always", [(set ABRegs:$dst, (TeakShiftLogic ABRegs:$src, SVReg:$shift))]>;
|
||||
|
||||
let Defs = [ICC] in
|
||||
def SHFC_arith_ab_ab_sv : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$src, SVReg:$shift),
|
||||
"shfc $src, $dst, always",
|
||||
[(set ABRegs:$dst, (TeakShiftArith ABRegs:$src, SVReg:$shift))]>;
|
||||
def MPY_y0_regnob16 : InstTeak<(outs P0Regs:$p), (ins Y0Regs:$y, RegNoBRegs16:$x), "mpy $y, $x", []>;
|
||||
|
||||
let Defs = [ICC] in
|
||||
def SHFC_logic_ab_ab_sv : TeakPseudoInst<
|
||||
(outs ABRegs:$dst),
|
||||
(ins ABRegs:$src, SVReg:$shift),
|
||||
"shfc $src, $dst, always",
|
||||
[(set ABRegs:$dst, (TeakShiftLogic ABRegs:$src, SVReg:$shift))]>;
|
||||
let Defs = [ICC, P0] in
|
||||
def MPY_y0_regnob16_RegNoBRegs16 : TeakPseudoInst<(outs RegNoBRegs16:$dst), (ins Y0Regs:$y, RegNoBRegs16:$x), "mpy $y, $x", [(set RegNoBRegs16:$dst, (mul RegNoBRegs16:$x, Y0Regs:$y))]>;
|
||||
|
||||
// let Defs = [ICC, SV] in
|
||||
// def SRL_PSEUDO_ab_ab_sv : TeakPseudoInst<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, RegNoBRegs16:$shift),
|
||||
// "SRL_PSEUDO_ab_sv",
|
||||
// [(set ABRegs:$dst, (srl ABRegs:$x, RegNoBRegs16:$y))]>;
|
||||
|
||||
// let Defs = [ICC, SV] in
|
||||
// def SRA_PSEUDO_ab_ab_sv : TeakPseudoInst<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, RegNoBRegs16:$shift),
|
||||
// "SRA_PSEUDO_ab_sv",
|
||||
// [(set ABRegs:$dst, (sra ABRegs:$x, RegNoBRegs16:$y))]>;
|
||||
|
||||
// let Defs = [ICC, SV] in
|
||||
// def SHL_PSEUDO_ab_ab_sv : TeakPseudoInst<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, RegNoBRegs16:$shift),
|
||||
// "SHL_PSEUDO_ab_sv",
|
||||
// [(set ABRegs:$dst, (shl ABRegs:$x, RegNoBRegs16:$y))]>;
|
||||
|
||||
// let Defs = [ICC] in
|
||||
// def SHFI_ab_ab : InstTeak<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, imm0_31:$shift),
|
||||
// "shfi $src, $dst, -$shift",
|
||||
// [(set ABRegs:$dst, (sra ABRegs:$src, imm0_31:$shift))]>;
|
||||
|
||||
// let Defs = [ICC] in
|
||||
// def SHFI2_ab_ab : InstTeak<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, imm0_31:$shift),
|
||||
// "shfi $src, $dst, +$shift",
|
||||
// [(set ABRegs:$dst, (shl ABRegs:$src, imm0_31:$shift))]>;
|
||||
|
||||
// let Defs = [ICC] in
|
||||
// def SHFI3_ab_ab : InstTeak<
|
||||
// (outs ABRegs:$dst),
|
||||
// (ins ABRegs:$src, imm0_31:$shift),
|
||||
// "shfi $src, $dst, -$shift",
|
||||
// [(set ABRegs:$dst, (srl ABRegs:$src, imm0_31:$shift))]>;
|
||||
|
||||
let Defs = [ICC] in
|
||||
def MPY_y0_regnob16 : InstTeak<
|
||||
(outs P0Regs:$p),
|
||||
(ins Y0Regs:$y, RegNoBRegs16:$x),
|
||||
"mpy $y, $x",
|
||||
[]>;
|
||||
|
||||
let Defs = [ICC, P0] in
|
||||
def MPY_y0_regnob16_RegNoBRegs16 : TeakPseudoInst<
|
||||
(outs RegNoBRegs16:$dst),
|
||||
(ins Y0Regs:$y, RegNoBRegs16:$x),
|
||||
"mpy $y, $x",
|
||||
[(set RegNoBRegs16:$dst, (mul RegNoBRegs16:$x, Y0Regs:$y))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$asrc = $bdst, $bsrc = $adst" in
|
||||
def SWAP_ab : InstTeak<
|
||||
(outs BRegs:$adst, ARegs:$bdst),
|
||||
(ins ARegs:$asrc, BRegs:$bsrc),
|
||||
"swap ($asrc, $bsrc)",
|
||||
[]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def XOR_imm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins imm0_65535:$val, ARegs:$a),
|
||||
"xor $val, $a",
|
||||
[(set ARegs:$dst, (xor ARegs:$a, imm0_65535:$val))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def XOR_regnobp016_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins RegNoBRegs16:$b, ARegs:$a),
|
||||
"xor $b, $a",
|
||||
[(set ARegs:$dst, (xor ARegs:$a, (zext RegNoBRegs16:$b)))]>;
|
||||
|
||||
let Defs = [ICC], Constraints = "$dst = $a" in
|
||||
def XOR_a_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins ARegs:$b, ARegs:$a),
|
||||
"xor $b, $a",
|
||||
[(set ARegs:$dst, (xor ARegs:$a, ARegs:$b))]>;
|
||||
let Constraints = "$asrc = $bdst, $bsrc = $adst" in
|
||||
def SWAP_ab : InstTeak<(outs BRegs:$adst, ARegs:$bdst), (ins ARegs:$asrc, BRegs:$bsrc), "swap ($asrc, $bsrc)", []>;
|
||||
}
|
||||
|
||||
// def PseudoSRA : InstTeak<(outs ABRegs:$dst), (ins ABRegs:$src, Operand<i32>:$shift), "",
|
||||
// [(set i40:$dst, ( imm:$src))]> {
|
||||
@ -412,32 +225,24 @@ def XOR_a_a : InstTeakImm16<
|
||||
|
||||
//def : Pat<(i16 (add RegNoBRegs16:$a, RegNoBRegs16:$b)), (EXTRACT_SUBREG (ADD_regnobp016_a RegNoBRegs16:$a, (MOV_regnobp016_ab RegNoBRegs16:$b)), sub_16bit)>;
|
||||
|
||||
def LO16 : SDNodeXForm<imm, [{
|
||||
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 0xFFFF, SDLoc(N),
|
||||
MVT::i40);
|
||||
def LO16 : SDNodeXForm<imm,
|
||||
[{
|
||||
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 0xFFFF, SDLoc(N), MVT::i40);
|
||||
}]>;
|
||||
|
||||
def HI16 : SDNodeXForm<imm, [{
|
||||
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, SDLoc(N),
|
||||
MVT::i40);
|
||||
def HI16 : SDNodeXForm<imm,
|
||||
[{
|
||||
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, SDLoc(N), MVT::i40);
|
||||
}]>;
|
||||
|
||||
// Arbitrary immediates.
|
||||
def : Pat<(i40 imm:$val), (SET_imm16_abl (LO16 imm:$val), (MOV_imm16hi_ab (HI16 imm:$val)))>;
|
||||
|
||||
let mayStore = 1 in
|
||||
def MOV_al2_memimm16 : InstTeakImm16<
|
||||
(outs),
|
||||
(ins ALRegs:$a, Operand<i16>:$dstAddr),
|
||||
"mov ${a}, [$dstAddr]",
|
||||
[(store ALRegs:$a, imm:$dstAddr)]>;
|
||||
def MOV_al2_memimm16 : InstTeakImm16<(outs), (ins ALRegs:$a, Operand<i16>:$dstAddr), "mov ${a}, [$dstAddr]", [(store ALRegs:$a, imm:$dstAddr)]>;
|
||||
|
||||
let mayStore = 1 in
|
||||
def MOV_al_memimm16 : InstTeakImm16<
|
||||
(outs),
|
||||
(ins ARegs:$a, Operand<i16>:$dstAddr),
|
||||
"mov ${a}l, [$dstAddr]",
|
||||
[(truncstorei16 ARegs:$a, imm:$dstAddr)]>;
|
||||
def MOV_al_memimm16 : InstTeakImm16<(outs), (ins ARegs:$a, Operand<i16>:$dstAddr), "mov ${a}l, [$dstAddr]", [(truncstorei16 ARegs:$a, imm:$dstAddr)]>;
|
||||
|
||||
// let mayStore = 1 in
|
||||
// def MOV_al_memimm16 : InstTeak<
|
||||
@ -447,46 +252,22 @@ def MOV_al_memimm16 : InstTeakImm16<
|
||||
// [(store ALRegs:$a, tglobaladdr:$dstAddr)]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def MOV_memimm16_a : InstTeakImm16<
|
||||
(outs ARegs:$dst),
|
||||
(ins Operand<i16>:$srcAddr),
|
||||
"mov [$srcAddr], $dst",
|
||||
[(set ARegs:$dst, (sextloadi16 imm:$srcAddr))]>;
|
||||
def MOV_memimm16_a : InstTeakImm16<(outs ARegs:$dst), (ins Operand<i16>:$srcAddr), "mov [$srcAddr], $dst", [(set ARegs:$dst, (sextloadi16 imm:$srcAddr))]>;
|
||||
|
||||
let mayStore = 1 in
|
||||
def MOV_regnob16_memrn : InstTeak<
|
||||
(outs),
|
||||
(ins RegNoBRegs16:$a, GRRegs:$dstAddr),
|
||||
"mov $a, [$dstAddr]",
|
||||
[(store RegNoBRegs16:$a, GRRegs:$dstAddr)]>;
|
||||
def MOV_regnob16_memrn : InstTeak<(outs), (ins RegNoBRegs16:$a, GRRegs:$dstAddr), "mov $a, [$dstAddr]", [(store RegNoBRegs16:$a, GRRegs:$dstAddr)]>;
|
||||
|
||||
let mayStore = 1 in
|
||||
def MOV_abl_memrn : InstTeak<
|
||||
(outs),
|
||||
(ins ABRegs:$a, GRRegs:$dstAddr),
|
||||
"mov ${a}l, [$dstAddr]",
|
||||
[(truncstorei16 ABRegs:$a, GRRegs:$dstAddr)]>;
|
||||
def MOV_abl_memrn : InstTeak<(outs), (ins ABRegs:$a, GRRegs:$dstAddr), "mov ${a}l, [$dstAddr]", [(truncstorei16 ABRegs:$a, GRRegs:$dstAddr)]>;
|
||||
|
||||
let Defs = [ICC], mayLoad = 1 in
|
||||
def MOV_memrn_regnob16 : InstTeak<
|
||||
(outs RegNoBRegs16_nolh:$dst),
|
||||
(ins GRRegs:$srcAddr),
|
||||
"mov [$srcAddr], $dst",
|
||||
[(set RegNoBRegs16_nolh:$dst, (load GRRegs:$srcAddr))]>;
|
||||
def MOV_memrn_regnob16 : InstTeak<(outs RegNoBRegs16_nolh:$dst), (ins GRRegs:$srcAddr), "mov [$srcAddr], $dst", [(set RegNoBRegs16_nolh:$dst, (load GRRegs:$srcAddr))]>;
|
||||
|
||||
let Defs = [ICC], mayLoad = 1 in
|
||||
def MOV_memrn_ab : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins GRRegs:$srcAddr),
|
||||
"mov [$srcAddr], $dst",
|
||||
[(set ABRegs:$dst, (sextloadi16 GRRegs:$srcAddr))]>;
|
||||
def MOV_memrn_ab : InstTeak<(outs ABRegs:$dst), (ins GRRegs:$srcAddr), "mov [$srcAddr], $dst", [(set ABRegs:$dst, (sextloadi16 GRRegs:$srcAddr))]>;
|
||||
|
||||
let Defs = [ICC], mayLoad = 1 in
|
||||
def MOV_memrn_ab1 : InstTeak<
|
||||
(outs ABRegs:$dst),
|
||||
(ins GRRegs:$srcAddr),
|
||||
"mov [$srcAddr], ${dst}l",
|
||||
[(set ABRegs:$dst, (zextloadi16 GRRegs:$srcAddr))]>;
|
||||
def MOV_memrn_ab1 : InstTeak<(outs ABRegs:$dst), (ins GRRegs:$srcAddr), "mov [$srcAddr], ${dst}l", [(set ABRegs:$dst, (zextloadi16 GRRegs:$srcAddr))]>;
|
||||
|
||||
// anyextload
|
||||
def : Pat<(extloadi16 GRRegs:$srcAddr), (MOV_memrn_ab1 GRRegs:$srcAddr)>;
|
||||
@ -500,60 +281,28 @@ def : Pat<(extloadi16 tglobaladdr:$srcAddr), (MOV_memimm16_a i16:$srcAddr)>;
|
||||
// [(truncstorei16 ARegs:$a, addr:$offset)]>;
|
||||
|
||||
let mayStore = 1 in
|
||||
def MOV_a_r7offset16 : InstTeakImm16<
|
||||
(outs),
|
||||
(ins ARegs:$a, memsrc:$offset),
|
||||
"mov ${a}l, $offset",
|
||||
[]>;
|
||||
def MOV_a_r7offset16 : InstTeakImm16<(outs), (ins ARegs:$a, memsrc:$offset), "mov ${a}l, $offset", []>;
|
||||
|
||||
let Defs = [ICC], mayStore = 1 in
|
||||
def STORE_REG_TO_STACK_PSEUDO_16 : TeakPseudoInst<
|
||||
(outs),
|
||||
(ins RegNoBRegs16:$a, memsrc:$offset),
|
||||
"STORE_REG_TO_STACK_PSEUDO_16",
|
||||
[(store RegNoBRegs16:$a, addr:$offset)]>;
|
||||
def STORE_REG_TO_STACK_PSEUDO_16 : TeakPseudoInst<(outs), (ins RegNoBRegs16:$a, memsrc:$offset), "STORE_REG_TO_STACK_PSEUDO_16", [(store RegNoBRegs16:$a, addr:$offset)]>;
|
||||
|
||||
let Defs = [ICC], mayStore = 1 in
|
||||
def STORE_REG_TO_STACK_PSEUDO_TRUNC16 : TeakPseudoInst<
|
||||
(outs),
|
||||
(ins ABRegs:$a, memsrc:$offset),
|
||||
"STORE_REG_TO_STACK_PSEUDO_TRUNC16",
|
||||
[(truncstorei16 ABRegs:$a, addr:$offset)]>;
|
||||
def STORE_REG_TO_STACK_PSEUDO_TRUNC16 : TeakPseudoInst<(outs), (ins ABRegs:$a, memsrc:$offset), "STORE_REG_TO_STACK_PSEUDO_TRUNC16", [(truncstorei16 ABRegs:$a, addr:$offset)]>;
|
||||
|
||||
let Defs = [ICC], mayStore = 1 in
|
||||
def STORE_REG_TO_STACK_PSEUDO_32 : TeakPseudoInst<
|
||||
(outs),
|
||||
(ins ABRegs:$a, memsrc:$offset),
|
||||
"STORE_REG_TO_STACK_PSEUDO_32",
|
||||
[(truncstorei32 ABRegs:$a, addr:$offset)]>;
|
||||
def STORE_REG_TO_STACK_PSEUDO_32 : TeakPseudoInst<(outs), (ins ABRegs:$a, memsrc:$offset), "STORE_REG_TO_STACK_PSEUDO_32", [(truncstorei32 ABRegs:$a, addr:$offset)]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16 : TeakPseudoInst<
|
||||
(outs RegNoBRegs16:$a),
|
||||
(ins memsrc:$offset),
|
||||
"LOAD_REG_FROM_STACK_PSEUDO_16",
|
||||
[(set RegNoBRegs16:$a, (load addr:$offset))]>;
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16 : TeakPseudoInst<(outs RegNoBRegs16:$a), (ins memsrc:$offset), "LOAD_REG_FROM_STACK_PSEUDO_16", [(set RegNoBRegs16:$a, (load addr:$offset))]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40 : TeakPseudoInst<
|
||||
(outs ABRegs:$a),
|
||||
(ins memsrc:$offset),
|
||||
"LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40",
|
||||
[(set ABRegs:$a, (sextloadi16 addr:$offset))]>;
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40 : TeakPseudoInst<(outs ABRegs:$a), (ins memsrc:$offset), "LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40", [(set ABRegs:$a, (sextloadi16 addr:$offset))]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40 : TeakPseudoInst<
|
||||
(outs ABRegs:$a),
|
||||
(ins memsrc:$offset),
|
||||
"LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40",
|
||||
[(set ABRegs:$a, (zextloadi16 addr:$offset))]>;
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40 : TeakPseudoInst<(outs ABRegs:$a), (ins memsrc:$offset), "LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40", [(set ABRegs:$a, (zextloadi16 addr:$offset))]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40 : TeakPseudoInst<
|
||||
(outs ABRegs:$a),
|
||||
(ins memsrc:$offset),
|
||||
"LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40",
|
||||
[(set ABRegs:$a, (extloadi32 addr:$offset))]>;
|
||||
def LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40 : TeakPseudoInst<(outs ABRegs:$a), (ins memsrc:$offset), "LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40", [(set ABRegs:$a, (extloadi32 addr:$offset))]>;
|
||||
|
||||
//def : Pat<(extloadi32 memsrc:$offset), (LOAD_REG_FROM_STACK_PSEUDO_32_ZEXT40 addr:$offset)>;
|
||||
|
||||
@ -565,23 +314,14 @@ def LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40 : TeakPseudoInst<
|
||||
// [(store i16:$a, addr:$offset)]>;
|
||||
|
||||
let mayLoad = 1, Defs = [ICC] in
|
||||
def MOV_r7offset16_a : InstTeakImm16<
|
||||
(outs ARegs:$a),
|
||||
(ins memsrc:$offset),
|
||||
"mov $offset, ${a}",
|
||||
[]>;
|
||||
def MOV_r7offset16_a : InstTeakImm16<(outs ARegs:$a), (ins memsrc:$offset), "mov $offset, ${a}", []>;
|
||||
|
||||
|
||||
def : Pat<(truncstorei16 ARegs:$src, tglobaladdr:$dstAddr), (MOV_al_memimm16 (EXTRACT_SUBREG $src, sub_16bit), i16:$dstAddr)>;
|
||||
def : Pat<(truncstorei16 ABRegs:$src, GRRegs:$dstAddr), (MOV_regnob16_memrn (EXTRACT_SUBREG $src, sub_16bit), GRRegs:$dstAddr)>;
|
||||
|
||||
|
||||
|
||||
def : Pat<(i16 (trunc ABRegs:$src)),
|
||||
(EXTRACT_SUBREG ABRegs:$src, sub_16bit)>;
|
||||
|
||||
def : Pat<(i40 (anyext ABLRegs:$src)),
|
||||
(INSERT_SUBREG (i40 (IMPLICIT_DEF)), ABLRegs:$src, sub_16bit)>;
|
||||
def : Pat<(i16 (trunc ABRegs:$src)), (EXTRACT_SUBREG ABRegs:$src, sub_16bit)>;
|
||||
def : Pat<(i40 (anyext ABLRegs:$src)), (INSERT_SUBREG (i40 (IMPLICIT_DEF)), ABLRegs:$src, sub_16bit)>;
|
||||
|
||||
let Defs = [SP], Uses = [SP] in
|
||||
{
|
||||
@ -601,90 +341,56 @@ let Defs = [SP], Uses = [SP] in
|
||||
|
||||
let isCompare = 1, Defs = [ICC] in
|
||||
{
|
||||
def CMP_imm16_a : InstTeakImm16<
|
||||
(outs),
|
||||
(ins immNeg32768_32767:$val, ARegs:$a),
|
||||
"cmp $val, $a",
|
||||
[(TeakCmpICC ARegs:$a, immNeg32768_32767:$val)]>;
|
||||
def CMP_imm8u_a : InstTeak <(outs), (ins Imm8u:$val, ARegs:$a), "cmp ${val}u8, $a", [(TeakCmpICC ARegs:$a, Imm8u:$val)]>;
|
||||
def CMP_imm16_a : InstTeakImm16<(outs), (ins immNeg32768_32767:$val, ARegs:$a), "cmp $val, $a", [(TeakCmpICC ARegs:$a, immNeg32768_32767:$val)]>;
|
||||
def CMPV_imm16_RegNoBRegs16 : InstTeakImm16<(outs), (ins immNeg32768_32767:$val, RegNoBRegs16:$a), "cmpv $val, $a", [(TeakCmpICC (sext RegNoBRegs16:$a), immNeg32768_32767:$val)]>;
|
||||
|
||||
let mayLoad = 1 in
|
||||
{
|
||||
def CMP_memimm16_a : InstTeakImm16<(outs), (ins Operand<i16>:$addr, ARegs:$a), "cmp [$addr], $a", [(TeakCmpICC ARegs:$a, (sextloadi16 imm:$addr))]>;
|
||||
def CMP_memrn_a : InstTeak<(outs), (ins GRRegs:$addr, ARegs:$a), "cmp [$addr], $a", [(TeakCmpICC ARegs:$a, (sextloadi16 GRRegs:$addr))]>;
|
||||
def CMPU_memrn_a : InstTeak<(outs), (ins GRRegs:$addr, ARegs:$a), "cmpu [$addr], $a", [(TeakCmpICC ARegs:$a, (zextloadi16 GRRegs:$addr))]>;
|
||||
}
|
||||
|
||||
def CMPV_imm16_RegNoBRegs16 : InstTeakImm16<
|
||||
(outs),
|
||||
(ins immNeg32768_32767_16:$val, RegNoBRegs16:$a),
|
||||
"cmpv $val, $a",
|
||||
[(TeakCmpICC RegNoBRegs16:$a, immNeg32768_32767_16:$val)]>;
|
||||
|
||||
def CMP_regnobp016_a : InstTeak<
|
||||
(outs),
|
||||
(ins RegNoBRegs16:$b, ARegs:$a),
|
||||
"cmp $b, $a",
|
||||
[(TeakCmpICC ARegs:$a, (sext RegNoBRegs16:$b))]>;
|
||||
|
||||
def CMPU_regnob016_a : InstTeak<
|
||||
(outs),
|
||||
(ins RegNoBRegs16:$b, ARegs:$a),
|
||||
"cmpu $b, $a",
|
||||
[(TeakCmpICC ARegs:$a, (zext RegNoBRegs16:$b))]>;
|
||||
|
||||
def CMP_ab_ab : InstTeak<
|
||||
(outs),
|
||||
(ins ABRegs:$b, ABRegs:$a),
|
||||
"cmp $b, $a",
|
||||
[(TeakCmpICC ABRegs:$a, ABRegs:$b)]>;
|
||||
def CMP_regnobp016_a : InstTeak<(outs), (ins RegNoBRegs16:$b, ARegs:$a), "cmp $b, $a", [(TeakCmpICC ARegs:$a, (sext RegNoBRegs16:$b))]>;
|
||||
def CMPU_regnob016_a : InstTeak<(outs), (ins RegNoBRegs16:$b, ARegs:$a), "cmpu $b, $a", [(TeakCmpICC ARegs:$a, (zext RegNoBRegs16:$b))]>;
|
||||
def CMP_ab_ab : InstTeak<(outs), (ins ABRegs:$b, ABRegs:$a), "cmp $b, $a", [(TeakCmpICC ABRegs:$a, ABRegs:$b)]>;
|
||||
}
|
||||
|
||||
let Uses = [ICC], usesCustomInserter = 1 in {
|
||||
def SELECT_CC_Int_ICC
|
||||
: TeakPseudoInst<(outs ABRegs:$dst), (ins ABRegs:$T, ABRegs:$F, Operand<i40>:$Cond),
|
||||
"; SELECT_CC_Int_ICC PSEUDO!",
|
||||
[(set i40:$dst, (TeakSelectICC i40:$T, i40:$F, imm:$Cond))]>;
|
||||
let Uses = [ICC], usesCustomInserter = 1 in
|
||||
{
|
||||
def SELECT_CC_Int_ICC : TeakPseudoInst<(outs ABRegs:$dst), (ins ABRegs:$T, ABRegs:$F, Operand<i40>:$Cond), "; SELECT_CC_Int_ICC PSEUDO!",
|
||||
[(set i40:$dst, (TeakSelectICC i40:$T, i40:$F, imm:$Cond))]>;
|
||||
|
||||
def SELECT_CC_Int_ICC_i16
|
||||
: TeakPseudoInst<(outs GRRegs:$dst), (ins RegNoBRegs16:$T, RegNoBRegs16:$F, Operand<i40>:$Cond),
|
||||
"; SELECT_CC_Int_ICC PSEUDO!",
|
||||
[(set GRRegs:$dst, (TeakSelectICC RegNoBRegs16:$T, RegNoBRegs16:$F, imm:$Cond))]>;
|
||||
def SELECT_CC_Int_ICC_i16 : TeakPseudoInst<(outs GRRegs:$dst), (ins RegNoBRegs16:$T, RegNoBRegs16:$F, Operand<i40>:$Cond), "; SELECT_CC_Int_ICC PSEUDO!",
|
||||
[(set GRRegs:$dst, (TeakSelectICC RegNoBRegs16:$T, RegNoBRegs16:$F, imm:$Cond))]>;
|
||||
}
|
||||
|
||||
let Uses = [ICC], isBranch = 1, isTerminator = 1 in {
|
||||
def BRCond_imm18 : InstTeakImm16<(outs), (ins Operand<OtherVT>:$addr, CCOp:$cond),
|
||||
"br $addr, $cond",
|
||||
[(TeakBRICC bb:$addr, imm:$cond)]> {
|
||||
}
|
||||
}
|
||||
let Uses = [ICC], isBranch = 1, isTerminator = 1 in
|
||||
def BRCond_imm18 : InstTeakImm16<(outs), (ins Operand<OtherVT>:$addr, CCOp:$cond), "br $addr, $cond", [(TeakBRICC bb:$addr, imm:$cond)]>;
|
||||
|
||||
let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
|
||||
def BR_imm18 : InstTeakImm16<(outs), (ins Operand<OtherVT>:$addr),
|
||||
"br $addr, always",
|
||||
[(br bb:$addr)]> {
|
||||
}
|
||||
}
|
||||
let isBarrier = 1, isBranch = 1, isTerminator = 1 in
|
||||
def BR_imm18 : InstTeakImm16<(outs), (ins Operand<OtherVT>:$addr), "br $addr, always", [(br bb:$addr)]>;
|
||||
|
||||
let isCall = 1, Defs = [SP], Uses = [SP] in {
|
||||
def CALL_imm : InstTeakImm16<(outs), (ins Operand<i40>:$addr),
|
||||
"call $addr, always",
|
||||
[(teak_call tglobaladdr:$addr)]> {
|
||||
}
|
||||
}
|
||||
let isCall = 1, Defs = [SP], Uses = [SP] in
|
||||
def CALL_imm : InstTeakImm16<(outs), (ins Operand<i40>:$addr), "call $addr, always", [(teak_call tglobaladdr:$addr)]>;
|
||||
|
||||
let isTerminator = 1, isReturn = 1, isBarrier = 1, Defs = [SP], Uses = [SP], mayLoad = 1 in {
|
||||
def RET : InstTeak<(outs), (ins),
|
||||
"ret always", [(TeakRetFlag)]> {
|
||||
//let Inst{27-0} = 0b0001001011111111111100011110;
|
||||
}
|
||||
}
|
||||
let isTerminator = 1, isReturn = 1, isBarrier = 1, Defs = [SP], Uses = [SP], mayLoad = 1 in
|
||||
def RET : InstTeak<(outs), (ins), "ret always", [(TeakRetFlag)]>;
|
||||
|
||||
let Defs = [SP], Uses = [SP] in {
|
||||
def ADJCALLSTACKDOWN : TeakPseudoInst<(outs), (ins i16imm:$amt, i16imm:$amt2),
|
||||
"# ADJCALLSTACKDOWN $amt, $amt2",
|
||||
[(callseq_start timm:$amt, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : TeakPseudoInst<(outs), (ins i16imm:$amt1, i16imm:$amt2),
|
||||
"# ADJCALLSTACKUP $amt1",
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
let Defs = [SP], Uses = [SP] in
|
||||
{
|
||||
def ADJCALLSTACKDOWN : TeakPseudoInst<(outs), (ins i16imm:$amt, i16imm:$amt2), "# ADJCALLSTACKDOWN $amt, $amt2", [(callseq_start timm:$amt, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : TeakPseudoInst<(outs), (ins i16imm:$amt1, i16imm:$amt2), "# ADJCALLSTACKUP $amt1", [(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
}
|
||||
|
||||
def RawAsmOp : InstTeak<(outs), (ins i16imm:$opcode), ".word $opcode", []>;
|
||||
def RawAsmOpExtended : InstTeakImm16<(outs), (ins i16imm:$opcode, i16imm:$ext), ".word $opcode, $ext", []>;
|
||||
|
||||
def : Pat<(i16 (TeakWrapper tglobaladdr:$dst)), (MOV_imm16_regnob16 tglobaladdr:$dst)>;
|
||||
def : Pat<(i40 (sextloadi16 (TeakWrapper tglobaladdr:$src))), (MOV_memimm16_a tglobaladdr:$src)>;
|
||||
def : Pat<(i40 (add ARegs:$a, (sextloadi16 (TeakWrapper tglobaladdr:$src)))), (ADD_memimm16_a tglobaladdr:$src, ARegs:$a)>;
|
||||
def : Pat<(i40 (and ARegs:$a, (zextloadi16 (TeakWrapper tglobaladdr:$src)))), (AND_memimm16_a tglobaladdr:$src, ARegs:$a)>;
|
||||
def : Pat<(TeakCmpICC ARegs:$a, (i40 (sextloadi16 (TeakWrapper tglobaladdr:$src)))), (CMP_memimm16_a tglobaladdr:$src, ARegs:$a)>;
|
||||
def : Pat<(store ALRegs:$src, (i16 (TeakWrapper tglobaladdr:$dst))), (MOV_al2_memimm16 ALRegs:$src, tglobaladdr:$dst)>;
|
||||
def : Pat<(truncstorei16 ARegs:$src, (i16 (TeakWrapper tglobaladdr:$dst))), (MOV_al_memimm16 ARegs:$src, tglobaladdr:$dst)>;
|
||||
def : Pat<(truncstorei16 ARegs:$src, (i16 (TeakWrapper tglobaladdr:$dst))), (MOV_al_memimm16 ARegs:$src, tglobaladdr:$dst)>;
|
||||
def : Pat<(i40 (sextloadi16 (TeakWrapper tglobaladdr:$src))), (MOV_memimm16_a tglobaladdr:$src)>;
|
||||
def : Pat<(i16 (TeakWrapper tglobaladdr:$dst)), (MOV_imm16_regnob16 tglobaladdr:$dst)>;
|
||||
@ -105,7 +105,7 @@ unsigned TeakRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, Ma
|
||||
default:
|
||||
return 0;
|
||||
case Teak::GRRegsRegClassID:
|
||||
return 5;
|
||||
return 6;
|
||||
case Teak::SVRegRegClassID:
|
||||
return 0;
|
||||
case Teak::ABRegsRegClassID:
|
||||
@ -115,7 +115,7 @@ unsigned TeakRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, Ma
|
||||
case Teak::ABLRegsRegClassID:
|
||||
return 4;
|
||||
case Teak::RegNoBRegs16_nohRegClassID:
|
||||
return 9;
|
||||
return 10;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -99,11 +99,11 @@ def ICC : TeakReg<0, "ICC">;//for flag setting ops, maybe rename
|
||||
|
||||
// Register classes.
|
||||
//
|
||||
def GRRegs : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R7)>;
|
||||
def GRRegs : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
|
||||
def RegNoBRegs40 : RegisterClass<"Teak", [i40], 32, (add A0, A1)>;
|
||||
def RegNoBRegs16 : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R7, Y0, SP, B0H, B1H, B0L, B1L, A0L, A1L, A0H, A1H, LC, SV)>;
|
||||
def RegNoBRegs16_nolh : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R7, Y0, SP, LC, SV)>;
|
||||
def RegNoBRegs16_noh : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R7, Y0, SP, A0L, A1L, B0L, B1L, LC, SV)>;
|
||||
def RegNoBRegs16 : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7, Y0, SP, B0H, B1H, B0L, B1L, A0L, A1L, A0H, A1H, LC, SV)>;
|
||||
def RegNoBRegs16_nolh : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7, Y0, SP, LC, SV)>;
|
||||
def RegNoBRegs16_noh : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7, Y0, SP, A0L, A1L, B0L, B1L, LC, SV)>;
|
||||
//def RegNoBRegsP040 : RegisterClass<"Teak", [i40], 32, (add A0, A1)>;
|
||||
//def RegNoBRegsP016 : RegisterClass<"Teak", [i16], 16, (add R0, R1, R2, R3, R4, R5, R7, Y0, /**/ SP, B0H, B1H, B0L, B1L, A0L, A1L, A0H, A1H, LC, SV)>;
|
||||
def ARegs : RegisterClass<"Teak", [i40], 32, (add A0, A1)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user