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Added section about hicode in technical reference manual
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docs/Technical Reference Manual/.gitignore
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docs/Technical Reference Manual/.gitignore
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*.out
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*.synctex.gz
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*.toc
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main-blx.bib
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*.bcf
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main.run.xml
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main.pdf
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docs/Technical Reference Manual/figures/icache.pdf
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\usepackage{hhline}
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\usepackage{bytefield}
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\usepackage{adjustbox}
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%\usepackage[table,xcdraw]{xcolor}
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\usepackage{makecell}
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\usepackage{todonotes}
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\usepackage{fontspec}
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\usepackage[backend=bibtex]{biblatex}
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\addbibresource{refs.bib}
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\setmainfont{Arial}
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\setmonofont{Consolas}
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\title{GBARunner 3\\Technical Reference Manual}
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\author{Gericom}
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\date{26 August 2023}
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% facilitates the creation of memory maps. Start address at the bottom, end address at the top.
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% syntax: \memsection{end address}{start address}{height in lines}{text in box}
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@ -61,143 +65,7 @@
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In this document various new ideas for GBARunner 3 will be documented, together with lessons learned from GBARunner 2 and the things that already worked well.
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\chapter{System Overview}
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In this chapter an overview will be given of the GBARunner 3 system, including block diagrams and memory maps.
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\newpage
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\section{Memory Map}
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\subsection{ARM 9}
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\begin{figure}[htb]
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\centering
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\begin{minipage}[t]{0.5\linewidth}%
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\hspace{-0.75cm}%
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\begin{bytefield}{24}
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\memsection{05FFFFFF}{05000800}{4}{Palette Mirrors}\\
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\memsection{050007FF}{05000600}{2}{Sub OBJ Palette (0.5 KB)}\\
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\memsection{050005FF}{05000400}{2}{Sub BG Palette (0.5 KB)}\\
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\memsection{050003FF}{05000200}{2}{GBA OBJ Palette (0.5 KB)}\\
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\memsection{050001FF}{05000000}{2}{GBA BG Palette (0.5 KB)}\\
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\memsection{04FFFFFF}{04000000}{4}{IO Registers}\\
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\memsection{03FFFFFF}{03008000}{4}{GBA IWRAM Mirrors}\\
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\memsection{03007FFF}{03000000}{2}{GBA IWRAM (32 KB)}\\
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\memsection{02FFFFFF}{02400000}{4}{Main Memory Mirrors}\\
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\memsection{023FFFFF}{02200000}{2}{JIT (linear 2 MB)}\\
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\memsection{021FFFFF}{021C0000}{2}{JIT (dynamic 256 KB)}\\
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\memsection{021BFFFF}{020C0000}{2}{SD Cache (1 MB)}\\
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\memsection{020BFFFF}{020A0000}{2}{Save (128 KB)}\\
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\memsection{0209FFFF}{02040000}{2}{GBARunner 3 Data (384 KB)}\\
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\memsection{0203FFFF}{02000000}{2}{GBA EWRAM (256 KB)}\\
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\memsection{01FFFFFF}{00008000}{4}{Unmapped}\\
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\memsection{00007FFF}{00000000}{2}{ITCM (32 KB)}
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\end{bytefield}
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\end{minipage}%
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\begin{minipage}[t]{0.5\linewidth}%
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\hspace{-0.75cm}%
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\begin{bytefield}{24}
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\memsection{FFFFFFFF}{FFFFC000}{2}{DTCM (16 KB)}\\
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\memsection{FFFFBFFF}{80000000}{4}{DTCM Mirrors}\\
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\memsection{7FFFFFFF}{08000000}{4}{Unmapped}\\
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\memsection{07FFFFFF}{07000800}{3}{OAM Mirrors}\\
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\memsection{070007FF}{07000400}{2}{Sub OAM (1 KB)}\\
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\memsection{070003FF}{07000000}{2}{GBA OAM (1 KB)}\\
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\memsection{}{}{2}{}\\
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\memsection{0683FFFF}{06820000}{2}{LCDC VRAM B (128 KB)}\\
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\memsection{0682FFFF}{06800000}{2}{LCDC VRAM A (128 KB)}\\
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\memsection{067FFFFF}{06600000}{3}{Sub OBJ VRAM}\\
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\memsection{065FFFFF}{06408000}{3}{Main OBJ VRAM Mirrors}\\
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\memsection{06407FFF}{06404000}{2}{GBA OBJ VRAM (G, 16 KB)}\\
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\memsection{06403FFF}{06400000}{2}{GBA OBJ VRAM (F, 16 KB)\footnote{For BG modes 0, 1 and 2}}\\
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\memsection{063FFFFF}{06200000}{3}{Sub BG VRAM}\\
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\memsection{061FFFFF}{06014000}{3}{Main BG VRAM Mirrors}\\
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\memsection{06013FFF}{06010000}{2}{GBA BG VRAM (F, 16 KB)\footnote{For BG modes 3, 4 and 5}}\\
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\memsection{0600FFFF}{06000000}{2}{GBA BG VRAM (E, 64 KB)}
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\end{bytefield}
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\end{minipage}%
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\caption{Physical ARM 9 memory map for GBARunner 3 running on regular DS hardware.}
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\end{figure}
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\section{Memory Protection Regions}
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Regions with a higher index take priority over regions with a lower index. When the ARM 9 is running in non-privileged user mode the rights from the ``user" column apply, when running in a privileged mode the rights from the ``system" column apply.
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\begin{table}[htb]
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\centering
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\begin{tabular}{l|l|l|l|l|l}
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\# & region & description & user & system & cache \& wrbuf \\ \hline
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7 & \texttt{02000000-0203FFFF} & GBA EWRAM & \texttt{R/W/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
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6 & \texttt{03000000-03FFFFFF} & GBA IWRAM & \texttt{R/W/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
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5 & \texttt{06800000-0683FFFF} & LCDC VRAM A, B & \texttt{-/-/-} & \texttt{R/W/X} & \texttt{i/d/wrbuf} \\
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2 & \texttt{06000000-067FFFFF} & VRAM & \texttt{R/-/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
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1 & \texttt{02000000-023FFFFF} & Main Memory & \texttt{R/-/X} & \texttt{R/W/X} & \texttt{i/d/wrbuf} \\
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0 & \texttt{00000000-FFFFFFFF} & ITCM, DTCM, uncached mmem, IO & \texttt{-/-/-} & \texttt{R/W/X} & \texttt{-/-/-}
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\end{tabular}
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\caption{Overview of the memory protection regions for GBARunner 3.}
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\end{table}
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\chapter{Virtual Machine}\label{chap_vm}
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To have more control over the running game GBARunner 3 will use a Virtual Machine (hereafter VM) in which the GBA code runs. All code inside the VM will run in user mode (non-privileged). The actual mode of the virtualized ARM core will be held in the state of the VM. An additional advantage of this is that emulating aborted memory access instructions is easier when all code runs in user mode. By using the VM the GBA code will not be able to fully turn off interrupts by using the CPSR I bit. In such a case the VM will not receive any interrupts, but interrupts that are essential for the functioning of GBARunner 3 can still be handled.
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\section{Sensitive Instructions}
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Sensitive instructions are instructions that can change the state of the virtualized processor and that the VM needs to emulate. For GBA code there are no sensitive Thumb instructions. The following ARM instructions are sensitive:
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\begin{description}[leftmargin=!,labelwidth=4.5cm]
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\item[\texttt{mrs reg, cpsr}] Needs to read the CPSR from the VM state (combined with flags in the actual CPSR register).
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\item[\texttt{mrs reg, spsr}] Needs to read the SPSR from the VM state.
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\item[\texttt{msr cpsr, ...}] When a MSR instruction changes any of the control bits the change needs to be emulated by the VM.
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\item[\texttt{msr spsr, ...}] Needs to write the SPSR in the VM state.
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\item[\texttt{\textit{ALU}s pc, ...}] The SPSR to CPSR copy needs to be emulated by the VM.
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\item[\texttt{ldm\textit{XX} reg, \{...\}\textasciicircum}] Loading to user mode registers needs to be emulated by the VM.
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\item[\texttt{stm\textit{XX} reg, \{...\}\textasciicircum}] Storing from user mode registers needs to be emulated by the VM.
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\item[\texttt{ldm\textit{XX} reg, \{..., pc\}\textasciicircum}] The SPSR to CPSR copy needs to be emulated by the VM.
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\end{description}
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Because none of these instructions will cause an exception when executed in user mode they need to be replaced by exception generating instructions. This will be the task of the JIT (see Chapter \ref{chap_jit}).
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\section{Undefined Instructions}
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To emulate sensitive instructions the VM will support undefined instructions that are drop-in replacements for the instructions. Additionally, the VM will support undefined instructions for unresolved branches.
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\begin{table}[htb]
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\begin{adjustbox}{center}
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\texttt{
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\arrayrulecolor{black}
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\begin{NiceTabular}{l|clll|cccccccccccccccccccccccccccc|}[colortbl-like]
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\hline
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MSR & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{R} & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{F} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{X} & \multicolumn{1}{c|}{C} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{R} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{12}{c|}{2nd op} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{F} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{X} & C \\ \cline{1-1} \cline{6-33}
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MRS & \multicolumn{4}{c|}{} & 0 & 0 & 0 & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{R} & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rd} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{R} & 1 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rd} & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & 0 & 0 & 0 & 0 \\ \cline{1-1} \cline{6-33}
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LDM\textasciicircum (usr) & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 1 & 0 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{0} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{P} & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{U} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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LDM\textasciicircum \{pc\} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & W \\ \cline{1-1} \cline{6-33}
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LDM \{pc\} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{0} & \multicolumn{15}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & W \\ \cline{1-1} \cline{6-33}
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STM\textasciicircum{} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 0 & 0 \\ \cline{1-1} \cline{6-33}
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STM Rn! & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 0 & 1 \\ \cline{1-1} \cline{6-33}
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ALU Rd=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
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ALU Rn=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
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ALU Rm=pc & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{8}{c|}{2nd op} & 1 & 1 & 1 & 1 \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rd} & \multicolumn{8}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
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B & \multicolumn{4}{c|}{} & 1 & 0 & 1 & \multicolumn{1}{c|}{0} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
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BL & \multicolumn{4}{c|}{} & 1 & 0 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
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LDR Rn=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{U} & 0 & 0 & 1 & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
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& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{U} & \multicolumn{12}{c|}{2nd op} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rd} \\ \cline{1-1} \cline{6-33}
|
||||
LDR Rd=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} \\ \cline{1-1} \cline{6-33}
|
||||
LDRH & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{4}{c|}{addr\_mode} & 1 & 0 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{addr\_mode} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
LDRSH & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{4}{c|}{addr\_mode} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{addr\_mode} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
BX & \multicolumn{4}{c|}{} & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rm} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{\multirow{-34}{*}{\begin{tabular}[c]{@{}c@{}}c\\ o\\ n\\ d\end{tabular}}} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rm} \\ \hline
|
||||
\end{NiceTabular}}
|
||||
\end{adjustbox}
|
||||
\caption{Overview of ARM instructions and their undefined substitutions emulated by the VM.}
|
||||
\end{table}
|
||||
|
||||
\chapter{JIT Patcher}\label{chap_jit}
|
||||
The purpose of the JIT patcher (hereafter JIT) is primarily to support the VM by replacing sensitive instructions by exception generating substitutes. Additionally, the JIT can fix CPU compatibility issues, fix relocation related issues and make it possible to execute code in higher areas of the ROM (also referred to as hicode). To minimize the overhead of the JIT, a couple of megabytes of the ROM (depending on the amount of available memory) will still be linearly loaded into memory, as was the case in GBARunner 2. To allow code outside this linearly loaded region to run there will also be a dynamic JIT cache. About 80~90\% of the games can run entirely from about 2MB of linearly loaded rom data. In such games it may be possible to run Thumb code without any JIT patches. The only critical patches are the ARM sensitive instruction patches, to make the VM work correctly.
|
||||
\chapter{Implementation challenges}
|
||||
\section{CPU compatibility issues}
|
||||
CPU compatibility issues exist because ARM7TDMI code is executed on an ARM946E-S core. While the ARM946E-S is backwards compatible in the defined behavior of instructions, its (in ARM terminology) unpredictable behavior (which means it depends on the CPU implementation) does differ to some extent. The following differences have been identified:
|
||||
\subsection{\texttt{LDR pc}, \texttt{LDM \{\dots,pc\}} \--- ARM/Thumb switching}
|
||||
@ -272,14 +140,14 @@
|
||||
\subsubsection{Impact}
|
||||
Unknown, but likely very small. It is unknown how the destroyed C and V flag values comes to be, so any dependence on it is a bug.
|
||||
|
||||
\section{Relocation issues}
|
||||
Relocation issues originate from the difference in \texttt{PC} value. Most often the \texttt{PC} is only used for pool reads, switch table reads and switch jumps. The short range of those operations minimize the impact, especially when most of the code is linearly loaded into memory, including the pools in the expected relative locations. Occasionally code might use the value of \texttt{PC} to construct a much larger address (outside the linearly loaded range of code), or a value for which the actual number is important. The latter case could for example be when the value is not used as address or is compared with some stored value.
|
||||
\section{Relocation issues}\label{sec:relocation}
|
||||
Relocation issues originate from the difference in \texttt{PC} value when code is executed at a different memory address than originally intended. Most often the \texttt{PC} is only used for pool reads, switch table reads and switch jumps. The short range of those operations minimize the impact, especially when most of the code is linearly loaded into memory, including the pools in the expected relative locations. Occasionally code might use the value of \texttt{PC} to construct a much larger address (outside the linearly loaded range of code), or a value for which the actual number is important. The latter case could for example be when the value is not used as address or is compared with some stored value.
|
||||
|
||||
\subsection{Example}
|
||||
\textit{Game Boy Advance Video - SpongeBob SquarePants - Volume 1} (MSSE) is a good example of a problematic game. In various places it constructs values by adding the \texttt{PC} to a value loaded from the pool (for whatever reason). The worst (breaking) example is the following:
|
||||
\begin{verbatim}
|
||||
080000F4 add r8, pc, #0x90 // r8 = 0x0800018C
|
||||
080000F8 ldm r8, {r0, r1, r2, r3}
|
||||
080000F8 ldmia r8, {r0-r3}
|
||||
080000FC add r0, r0, r8 // r0 = 0x0800018C + 0x1FD4784 = 0x09FD4910
|
||||
08000100 add r1, r1, r8 // r1 = 0x0800018C + 0x1FD479C = 0x09FD4928
|
||||
08000104 add r2, r2, r8 // r2 = 0x0800018C + 0x1FD479C = 0x09FD4928
|
||||
@ -293,7 +161,7 @@
|
||||
The first two instructions are fine. A \texttt{PC}-relative pool address is constructed and 4 words are loaded from it. Then it adds the pool address to the loaded values to construct high rom addresses (which seem to contain some information related to relocating code to IWRAM). If we now consider that we would have had a DS main memory address in the \texttt{PC}, for example \texttt{0x020400F4}. The pool address would become \texttt{0x0204018C}, which is fine, because it's in the linearly loaded range. Now the high rom addresses are constructed and result in values such as \texttt{0x04014910}. This is way outside the loaded range and leads to a crash. It is difficult, if not impossible, to catch all such out-of-range addresses and compute what the intended address was. Especially when they overlap with other existing areas of memory such as IWRAM or IO registers, or other GBARunner data in main memory.
|
||||
|
||||
\subsection{Impact}
|
||||
For code that is sufficiently linearly loaded into memory the impact is small and only a small number of games use the \texttt{PC} in a way that causes issues. For hicode that is loaded in small chunks into the dynamic JIT cache the issue is almost always present.
|
||||
For code that is sufficiently linearly loaded into memory the impact is small and only a small number of games use the \texttt{PC} in a way that causes issues. When code is loade in small chunks, for example into the sd cache or into a dynamic JIT cache, the issue is almost always present. An additional risk is that depending on the situation it may be difficult or impossible to translate return addresses back to the intended location, for example when a cache block has been replaced.
|
||||
|
||||
\subsection{Solution}
|
||||
A solution for this problem is to replace any instruction that uses the \texttt{PC} in an unpredictable\footnote{Unpredictable in this case means that once the instruction is executed a register will contain a value that is different from the one that would originally have been there, and that could be used in any way by further instructions. Instructions such as \texttt{ldr Rd, [pc, \#imm]} are self-contained and we can know whether they are safe or not.} way or that results in the wrong value being loaded, by an exception generating instruction. The emulator will then execute the instruction with the original \texttt{PC} value and return to the code which will continue with the correct value. This results in the correct values and addresses being computed which can later unambiguously be aborted and emulated.
|
||||
@ -301,9 +169,263 @@
|
||||
\subsection{Impact of the solution}
|
||||
The performance of the patched code will be effected by the exception generating instructions and subsequent emulation.
|
||||
|
||||
\section{Hicode}
|
||||
Hicode is a term used to refer to code at an address above the part of the rom that is linearly loaded into memory by GBARunner. In most games the rom is linked to have a code segment (.text) at the beginning, followed by data segments. As long as the code segment is smaller than the linearly loaded part of the rom there are no issues. When more memory is available (DSi 16 MB, or 3DS 32 MB), hicode is as such much less likely to be an issue, but can still occur. Hicode might exist for the following reasons:
|
||||
\begin{itemize}
|
||||
\item It can happen that a game simply has a lot of code and as such exceeds the linearly loaded part of the rom;
|
||||
\item When games have veneers (linker inserted jumps, mainly from rom to iwram) some linker scripts might place them at the end of the rom;
|
||||
\item Rom hacks usually add custom code to the end of roms;
|
||||
\item If a rom has a scene intro, it is usually appended to the end of the rom;
|
||||
\item Some multiple-in-one games are almost a glued together combination of the individual games, which means there is a pattern like code1, data1, code2, data2, etc.;
|
||||
\item Some games just have a weird linker script.
|
||||
\end{itemize}
|
||||
|
||||
Hicode is an issue, because it is difficult in practice to execute small chunks of code at an arbitrary memory location. These issues are partly explained in Section \ref{sec:relocation}. In practice the issues come down to ambiguous relative memory accesses, relative jumps and return addresses that are hard to translate back to the correct address. Furthermore, relative jumps from the linearly loaded rom region
|
||||
must also be correctly translated to the dynamically loaded code chunks. This can also be a challenge because of overlapping ambiguous memory addresses. On the DSi and 3DS this is less of an issue, as the \texttt{0x0C000000} mirror of main memory makes it possible to disambiguate rom addresses to some extent.
|
||||
|
||||
\subsection{Impact}
|
||||
The size of the impact is related to the amount of available memory. Many games are not effected at all. Rom hacks are often effected because they append custom code to the end of the rom.
|
||||
|
||||
\subsection{Solution: Cache mapping}
|
||||
Cache mapping is a solution for hicode that has been experimentally tried in GBARunner 2 (but only for DSi and 3DS). By abusing the instruction cache it is possible to map one 4 kB chunk of code at an arbitrary 4 kB aligned memory location.
|
||||
|
||||
The instruction cache of the DS ARM 9 is a 4-way set associative cache with a total size of 8 kB (see Figure \ref{fig:icache}). Each of the four sets contains 64 cache lines of 32 bytes (8 words). Which cache line inside a set (index) is used depends on the memory address (bits 10-5, see Figure \ref{fig:icacheAddress}). Which of the four sets will be used is decided by the replacement algorithm when a cache line is loaded into the cache. Depending on the CP15 control register configuration either round-robin (0, 1, 2, 3, 0, 1, \dots) or pseudo-random replacement is used. Normally there are thus four possible locations in the cache for each memory address. It is additionally possible to lock up to three of the four sets, such that the cache lines in the locked sets will never be candidate for replacement. The intended use of this feature is to temporarily lock some important code (or data, as the data cache supports this as well) in the cache and prevent it from being replaced.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\begin{tabular}{|llllllllllllllllllllr|lllllr|llr|lr|}
|
||||
\footnotesize 31 & & & & & & & & & & & & & & & & & & & & \footnotesize 11 & \footnotesize 10 & & & & & \footnotesize 5 & \footnotesize 4 & & \footnotesize 2 & \footnotesize 1 & \footnotesize 0 \\ \hline
|
||||
\multicolumn{21}{|c|}{\Gape[0.3cm][0.3cm]{TAG}} & \multicolumn{6}{c|}{Index} & \multicolumn{3}{c|}{Word} & \multicolumn{2}{c|}{Byte} \\
|
||||
\hline
|
||||
\end{tabular}
|
||||
\caption{Overview of how an address is interpreted by the DS ARM 9 instruction cache \cite{arm946es_trm}.}
|
||||
\label{fig:icacheAddress}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[p]
|
||||
\centering
|
||||
\includegraphics[clip,trim=4.5cm 5cm 1cm 2cm,width=\linewidth]{figures/icache.pdf}
|
||||
\caption{Instruction cache architecture of the DS ARM 9 \cite{arm946es_trm}.}
|
||||
\label{fig:icache}
|
||||
\end{figure}
|
||||
|
||||
The instruction cache is controlled by the following CP15 instructions:
|
||||
\begin{description}
|
||||
\item[\texttt{mcr p15, 0, Rd, c7 , c5 , 0}] Invalidate (ARM: flush) entire instruction cache. \texttt{Rd} should be \texttt{0}.
|
||||
\item[\texttt{mcr p15, 0, Rd, c7 , c5 , 1}] Invalidate instruction cache line at address specified by \texttt{Rd}.
|
||||
\item[\texttt{mcr p15, 0, Rd, c7 , c13, 1}] Prefetch instruction cache line at address specified by \texttt{Rd}.
|
||||
\item[\texttt{mcr p15, 0, Rd, c9 , c0 , 1}] Write \textit{Instruction Lockdown Register}.
|
||||
\item[\texttt{mrc p15, 0, Rd, c9 , c0 , 1}] Read \textit{Instruction Lockdown Register}.
|
||||
\item[\texttt{mcr p15, 3, Rd, c15, c0 , 0}] Write \textit{Cache Debug Index Register}.
|
||||
\item[\texttt{mrc p15, 3, Rd, c15, c0 , 0}] Read \textit{Cache Debug Index Register}.
|
||||
\item[\texttt{mcr p15, 3, Rd, c15, c1 , 0}] Instruction TAG write.
|
||||
\item[\texttt{mrc p15, 3, Rd, c15, c1 , 0}] Instruction TAG read.
|
||||
\item[\texttt{mcr p15, 3, Rd, c15, c3 , 0}] Instruction cache write.
|
||||
\item[\texttt{mrc p15, 3, Rd, c15, c3 , 0}] Instruction cache read.
|
||||
\end{description}
|
||||
|
||||
For cache mapping especially the debug instructions are important. They allow us to alter the contents of the cache; in particular the TAG that specifies the upper part of the memory address a cache line belongs to. This makes it possible to have the cache contain instructions at a memory location where those instructions do not actually exist. To prevent these mapped instructions from being evicted from the cache, this must be combined with locking down the part of the cache the mapped instructions are in.
|
||||
|
||||
\subsubsection{How it works}
|
||||
The steps to map code are as follows:
|
||||
\begin{enumerate}
|
||||
\item First a 4 kB MPU region is setup at the target address. It should only allow instruction fetches, and have instruction cache enabled.
|
||||
|
||||
\item Next the instruction cache is switched in lockdown mode by writing to the CP15 \textit{Instruction Lockdown Register}.
|
||||
|
||||
\item The instructions are now loaded into the cache. When the source instructions are 2 kB aligned they can be quickly loaded into the cache using the instruction cache prefetch CP15 instruction (combined with the load flag in the \textit{Instruction Lockdown Register}). Otherwise, they must be written into the cache manually using the instruction cache write debug CP15 instruction. The reason for this is that part of the address determines the line index in the cache set (see Figure \ref{fig:icacheAddress}). When the source alignment is not right, the instructions will not end up at the right target address.
|
||||
|
||||
\item Finally the TAG of the loaded cache lines must be adjusted to contain the intended target address. This is done using the Instruction TAG write CP15 instruction. Note that this can be interleaved with loading the instructions into the cache.
|
||||
\end{enumerate}
|
||||
It is important to note that when the CP15 instruction is used to invalidate the entire instruction cache, this also invalidates the locked parts of the cache. When this happens, either the TAGs must be fixed up manually, or the cache mapping must be disabled by disabling cache lockdown and the protection region.
|
||||
|
||||
To map larger areas of memory the steps outlined above should be combined with a prefetch abort handler that will map the right chunk every time a jump outside the chunk is made. Note that additionally a data abort handler should be used, because data fetches cannot come from the instruction cache. The abort handler should take care to not read the aborted instruction with a regular load instruction as it will not fetch the right data. Instead the instruction can be read from the instruction cache with a debug CP15 instruction, or loaded from a different place in memory.
|
||||
|
||||
\subsubsection{Impact of the solution}
|
||||
Pros:
|
||||
\begin{itemize}
|
||||
\item Makes it possible to run code in dynamically loaded chunks.
|
||||
\item You can run code at the originally intended address (for example the 0x08000000 region for GBA roms), which prevents relocation issues.
|
||||
\item No patches or modifications of the code are required.
|
||||
\item It was shown to fix games and rom hacks in practice on DSi and 3DS.
|
||||
\end{itemize}
|
||||
Cons:
|
||||
\begin{itemize}
|
||||
\item Only one 4 kB chunk can be loaded at a time.
|
||||
\item Cannot map a chunk smaller than 4 kB, because 4 kB is the minimum size of a protection region.
|
||||
\item While cache mapping is active half of the instruction cache is unusable for other memory regions.
|
||||
\item Loading of a 4 kB chunk is slow. When a lot of code is executed with this method, there is a significant performance degradation. Worst case is a loop at a 4 kB boundary. Best performance is achieved if the source instructions are 2 kB aligned such that instruction prefetch can be used. The performance issue is slightly mitigated by the fact that the code runs directly from the cache and can run at maximum CPU speed.
|
||||
\item All pool reads must be aborted.
|
||||
\item Special case required in the data abort handler to fetch the aborted instruction from the instruction cache.
|
||||
\item When a mix of linearly loaded instructions and cache mapping is used, it is still necessary to be able to disambiguate relative jumps from the linear to the dynamic part.
|
||||
\end{itemize}
|
||||
|
||||
\subsection{Solution: JIT}
|
||||
When branches and pc-relative instructions are controlled by a JIT it becomes possible to run smaller chunks of code in a dynamic JIT cache.
|
||||
|
||||
\subsubsection{Impact of the solution}
|
||||
Pros:
|
||||
\begin{itemize}
|
||||
\item
|
||||
\end{itemize}
|
||||
Cons:
|
||||
\begin{itemize}
|
||||
\item
|
||||
\end{itemize}
|
||||
|
||||
\section{Graphics compatibility issues}
|
||||
\subsection{GBA bitmap modes 3, 4 and 5 stride}
|
||||
\subsubsection{Solution: Special affine matrix}
|
||||
|
||||
\subsection{GBA bitmap modes 3 and 5 alpha bit}
|
||||
\subsection{Sprite priorities}
|
||||
|
||||
\section{Sound issues}
|
||||
\subsection{ARM 7 cannot access sample data in IWRAM}
|
||||
|
||||
|
||||
\chapter{System overview}
|
||||
In this chapter an overview will be given of the GBARunner 3 system, including block diagrams and memory maps.
|
||||
\newpage
|
||||
\section{Memory map}
|
||||
\subsection{ARM 9}
|
||||
\begin{figure}[htb]
|
||||
\centering
|
||||
\begin{minipage}[t]{0.5\linewidth}%
|
||||
\hspace{-0.75cm}%
|
||||
\begin{bytefield}{24}
|
||||
\memsection{05FFFFFF}{05000800}{4}{Palette Mirrors}\\
|
||||
\memsection{050007FF}{05000600}{2}{Sub OBJ Palette (0.5 KB)}\\
|
||||
\memsection{050005FF}{05000400}{2}{Sub BG Palette (0.5 KB)}\\
|
||||
\memsection{050003FF}{05000200}{2}{GBA OBJ Palette (0.5 KB)}\\
|
||||
\memsection{050001FF}{05000000}{2}{GBA BG Palette (0.5 KB)}\\
|
||||
\memsection{04FFFFFF}{04000000}{4}{IO Registers}\\
|
||||
\memsection{03FFFFFF}{03008000}{4}{GBA IWRAM Mirrors}\\
|
||||
\memsection{03007FFF}{03000000}{2}{GBA IWRAM (32 KB)}\\
|
||||
\memsection{02FFFFFF}{02400000}{4}{Main Memory Mirrors}\\
|
||||
\memsection{023FFFFF}{02200000}{2}{JIT (linear 2 MB)}\\
|
||||
\memsection{021FFFFF}{021C0000}{2}{JIT (dynamic 256 KB)}\\
|
||||
\memsection{021BFFFF}{020C0000}{2}{SD Cache (1 MB)}\\
|
||||
\memsection{020BFFFF}{020A0000}{2}{Save (128 KB)}\\
|
||||
\memsection{0209FFFF}{02040000}{2}{GBARunner 3 Data (384 KB)}\\
|
||||
\memsection{0203FFFF}{02000000}{2}{GBA EWRAM (256 KB)}\\
|
||||
\memsection{01FFFFFF}{00008000}{4}{Unmapped}\\
|
||||
\memsection{00007FFF}{00000000}{2}{ITCM (32 KB)}
|
||||
\end{bytefield}
|
||||
\end{minipage}%
|
||||
\begin{minipage}[t]{0.5\linewidth}%
|
||||
\hspace{-0.75cm}%
|
||||
\begin{bytefield}{24}
|
||||
\memsection{FFFFFFFF}{FFFFC000}{2}{DTCM (16 KB)}\\
|
||||
\memsection{FFFFBFFF}{80000000}{4}{DTCM Mirrors}\\
|
||||
\memsection{7FFFFFFF}{08000000}{4}{Unmapped}\\
|
||||
\memsection{07FFFFFF}{07000800}{3}{OAM Mirrors}\\
|
||||
\memsection{070007FF}{07000400}{2}{Sub OAM (1 KB)}\\
|
||||
\memsection{070003FF}{07000000}{2}{GBA OAM (1 KB)}\\
|
||||
\memsection{}{}{2}{}\\
|
||||
\memsection{0683FFFF}{06820000}{2}{LCDC VRAM B (128 KB)}\\
|
||||
\memsection{0682FFFF}{06800000}{2}{LCDC VRAM A (128 KB)}\\
|
||||
\memsection{067FFFFF}{06600000}{3}{Sub OBJ VRAM}\\
|
||||
\memsection{065FFFFF}{06408000}{3}{Main OBJ VRAM Mirrors}\\
|
||||
\memsection{06407FFF}{06404000}{2}{GBA OBJ VRAM (G, 16 KB)}\\
|
||||
\memsection{06403FFF}{06400000}{2}{GBA OBJ VRAM (F, 16 KB)\footnote{For BG modes 0, 1 and 2}}\\
|
||||
\memsection{063FFFFF}{06200000}{3}{Sub BG VRAM}\\
|
||||
\memsection{061FFFFF}{06014000}{3}{Main BG VRAM Mirrors}\\
|
||||
\memsection{06013FFF}{06010000}{2}{GBA BG VRAM (F, 16 KB)\footnote{For BG modes 3, 4 and 5}}\\
|
||||
\memsection{0600FFFF}{06000000}{2}{GBA BG VRAM (E, 64 KB)}
|
||||
\end{bytefield}
|
||||
\end{minipage}%
|
||||
\caption{Physical ARM 9 memory map for GBARunner 3 running on regular DS hardware.}
|
||||
\end{figure}
|
||||
|
||||
\section{Memory protection regions}
|
||||
Regions with a higher index take priority over regions with a lower index. When the ARM 9 is running in non-privileged user mode the rights from the ``user" column apply, when running in a privileged mode the rights from the ``system" column apply.
|
||||
\begin{table}[htb]
|
||||
\centering
|
||||
\begin{tabular}{l|l|l|l|l|l}
|
||||
\# & region & description & user & system & cache \& wrbuf \\ \hline
|
||||
7 & \texttt{02000000-0203FFFF} & GBA EWRAM & \texttt{R/W/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
|
||||
6 & \texttt{03000000-03FFFFFF} & GBA IWRAM & \texttt{R/W/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
|
||||
5 & \texttt{06800000-0683FFFF} & LCDC VRAM A, B & \texttt{-/-/-} & \texttt{R/W/X} & \texttt{i/d/wrbuf} \\
|
||||
2 & \texttt{06000000-067FFFFF} & VRAM & \texttt{R/-/X} & \texttt{R/W/X} & \texttt{i/-/-} \\
|
||||
1 & \texttt{02000000-023FFFFF} & Main Memory & \texttt{R/-/X} & \texttt{R/W/X} & \texttt{i/d/wrbuf} \\
|
||||
0 & \texttt{00000000-FFFFFFFF} & ITCM, DTCM, uncached mmem, IO & \texttt{-/-/-} & \texttt{R/W/X} & \texttt{-/-/-}
|
||||
\end{tabular}
|
||||
\caption{Overview of the memory protection regions for GBARunner 3.}
|
||||
\end{table}
|
||||
|
||||
\chapter{Virtual machine}\label{chap_vm}
|
||||
To have more control over the running game GBARunner 3 will use a Virtual Machine (hereafter VM) in which the GBA code runs. All code inside the VM will run in user mode (non-privileged). The actual mode of the virtualized ARM core will be held in the state of the VM. An additional advantage of this is that emulating aborted memory access instructions is easier when all code runs in user mode. By using the VM the GBA code will not be able to fully turn off interrupts by using the CPSR I bit. In such a case the VM will not receive any interrupts, but interrupts that are essential for the functioning of GBARunner 3 can still be handled.
|
||||
|
||||
\section{Sensitive Instructions}
|
||||
Sensitive instructions are instructions that can change the state of the virtualized processor and that the VM needs to emulate. For GBA code there are no sensitive Thumb instructions. The following ARM instructions are sensitive:
|
||||
\begin{description}[leftmargin=!,labelwidth=4.5cm]
|
||||
\item[\texttt{mrs reg, cpsr}] Needs to read the CPSR from the VM state (combined with flags in the actual CPSR register).
|
||||
\item[\texttt{mrs reg, spsr}] Needs to read the SPSR from the VM state.
|
||||
\item[\texttt{msr cpsr, ...}] When a MSR instruction changes any of the control bits the change needs to be emulated by the VM.
|
||||
\item[\texttt{msr spsr, ...}] Needs to write the SPSR in the VM state.
|
||||
\item[\texttt{\textit{ALU}s pc, ...}] The SPSR to CPSR copy needs to be emulated by the VM.
|
||||
\item[\texttt{ldm\textit{XX} reg, \{...\}\textasciicircum}] Loading to user mode registers needs to be emulated by the VM.
|
||||
\item[\texttt{stm\textit{XX} reg, \{...\}\textasciicircum}] Storing from user mode registers needs to be emulated by the VM.
|
||||
\item[\texttt{ldm\textit{XX} reg, \{..., pc\}\textasciicircum}] The SPSR to CPSR copy needs to be emulated by the VM.
|
||||
\end{description}
|
||||
Because none of these instructions will cause an exception when executed in user mode they need to be replaced by exception generating instructions. This will be the task of the JIT (see Chapter \ref{chap_jit}).
|
||||
|
||||
\section{Undefined instructions}
|
||||
To emulate sensitive instructions the VM will support undefined instructions that are drop-in replacements for the instructions. Additionally, the VM will support undefined instructions for unresolved branches.
|
||||
|
||||
\begin{table}[htb]
|
||||
\begin{adjustbox}{center}
|
||||
\texttt{
|
||||
\arrayrulecolor{black}
|
||||
\begin{NiceTabular}{l|clll|cccccccccccccccccccccccccccc|}[colortbl-like]
|
||||
\hline
|
||||
MSR & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{R} & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{F} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{X} & \multicolumn{1}{c|}{C} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{R} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{12}{c|}{2nd op} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{F} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{X} & C \\ \cline{1-1} \cline{6-33}
|
||||
MRS & \multicolumn{4}{c|}{} & 0 & 0 & 0 & 1 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{R} & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rd} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{R} & 1 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rd} & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & 0 & 0 & 0 & 0 \\ \cline{1-1} \cline{6-33}
|
||||
LDM\textasciicircum (usr) & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 1 & 0 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{0} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{P} & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{U} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
LDM\textasciicircum \{pc\} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & W \\ \cline{1-1} \cline{6-33}
|
||||
LDM \{pc\} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{15}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{0} & \multicolumn{15}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{1} & W \\ \cline{1-1} \cline{6-33}
|
||||
STM\textasciicircum{} & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 0 & 0 \\ \cline{1-1} \cline{6-33}
|
||||
STM Rn! & \multicolumn{4}{c|}{} & 1 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} & \multicolumn{16}{c|}{rlist} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & 0 & 1 \\ \cline{1-1} \cline{6-33}
|
||||
ALU Rd=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
|
||||
ALU Rn=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{I} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
|
||||
ALU Rm=pc & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{4}{c|}{op} & \multicolumn{1}{c|}{S} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{8}{c|}{2nd op} & 1 & 1 & 1 & 1 \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rd} & \multicolumn{8}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{S} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{Rn} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{op} \\ \cline{1-1} \cline{6-33}
|
||||
B & \multicolumn{4}{c|}{} & 1 & 0 & 1 & \multicolumn{1}{c|}{0} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
|
||||
BL & \multicolumn{4}{c|}{} & 1 & 0 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{24}{c|}{offset} \\ \cline{1-1} \cline{6-33}
|
||||
LDR Rn=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{U} & 0 & 0 & 1 & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rd} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{U} & \multicolumn{12}{c|}{2nd op} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rd} \\ \cline{1-1} \cline{6-33}
|
||||
LDR Rd=pc & \multicolumn{4}{c|}{} & 0 & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{12}{c|}{2nd op} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{12}{c|}{2nd op} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rn} \\ \cline{1-1} \cline{6-33}
|
||||
LDRH & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{4}{c|}{addr\_mode} & 1 & 0 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{addr\_mode} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
LDRSH & \multicolumn{4}{c|}{} & 0 & 0 & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{4}{c|}{addr\_mode} & 1 & 1 & 1 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{4}{c|}{addr\_mode} & \multicolumn{4}{c|}{Rn} & \multicolumn{4}{c|}{Rd} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}0} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{P} & \multicolumn{1}{c|}{U} & \multicolumn{1}{c|}{I} & \multicolumn{1}{c|}{W} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{addr\_mode} \\ \cline{1-1} \cline{6-33}
|
||||
BX & \multicolumn{4}{c|}{} & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & \multicolumn{1}{c|}{1} & \multicolumn{4}{c|}{Rm} \\ \cline{1-1} \cline{6-33}
|
||||
& \multicolumn{4}{c|}{\multirow{-34}{*}{\begin{tabular}[c]{@{}c@{}}c\\ o\\ n\\ d\end{tabular}}} & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}1 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{0} & \cellcolor[HTML]{C0C0C0}1 & \cellcolor[HTML]{C0C0C0}0 & \cellcolor[HTML]{C0C0C0}0 & \multicolumn{1}{c|}{\cellcolor[HTML]{C0C0C0}1} & \multicolumn{4}{c|}{Rm} \\ \hline
|
||||
\end{NiceTabular}}
|
||||
\end{adjustbox}
|
||||
\caption{Overview of ARM instructions and their undefined substitutions emulated by the VM.
|
||||
\todo[inline]{TODO: Update this table. It is outdated.}}
|
||||
\end{table}
|
||||
|
||||
\chapter{JIT patcher}\label{chap_jit}
|
||||
The purpose of the JIT patcher (hereafter JIT) is primarily to support the VM by replacing sensitive instructions by exception generating substitutes. Additionally, the JIT can fix CPU compatibility issues, fix relocation related issues and make it possible to execute code in higher areas of the ROM (also referred to as hicode). To minimize the overhead of the JIT, a couple of megabytes of the ROM (depending on the amount of available memory) will still be linearly loaded into memory, as was the case in GBARunner 2. To allow code outside this linearly loaded region to run there will also be a dynamic JIT cache. About 80~90\% of the games can run entirely from about 2MB of linearly loaded rom data. In such games it may be possible to run Thumb code without any JIT patches. The only critical patches are the ARM sensitive instruction patches, to make the VM work correctly.
|
||||
|
||||
\section{Dynamic JIT cache}
|
||||
|
||||
\chapter{Memory Emulator}\label{chap_mememu}
|
||||
\chapter{Memory emulator}\label{chap_mememu}
|
||||
Various memory accesses need to be emulated to allow the GBA code to access the right data and registers. The ARM946E-S has no MMU (memory mapping unit), but it does have a MPU (memory protection unit) that can be used to protect up to 8 regions of memory. When a data abort happens the abort handler code emulates the memory instruction. The performance of the abort handler plays an important role in the performance of the entire system.
|
||||
\section{Memory Instructions}
|
||||
In this section an overview will be given of the instructions that need to be emulated.
|
||||
@ -403,12 +525,18 @@
|
||||
\end{tabular}}
|
||||
\caption{Overview of Thumb memory instructions that could cause an abort.}
|
||||
\end{table}
|
||||
\chapter{SD Cache}
|
||||
\chapter{SD cache}
|
||||
GBARunner 2 used a least-recently-used (LRU) cache. Using a simpler replacement algorithm such as pseudo-random might be more efficient in practice, because LRU requires an update to the cache block list for every access.
|
||||
\chapter{GBA Peripherals Emulation}
|
||||
\chapter{GBA peripherals emulation}
|
||||
\section{Graphics}
|
||||
\section{Timers}
|
||||
\section{Sound}
|
||||
\section{DMA}
|
||||
\section{SIO}
|
||||
|
||||
\clearpage
|
||||
{
|
||||
\raggedright
|
||||
\printbibliography
|
||||
}
|
||||
\end{document}
|
||||
9
docs/Technical Reference Manual/refs.bib
Normal file
9
docs/Technical Reference Manual/refs.bib
Normal file
@ -0,0 +1,9 @@
|
||||
@manual{arm946es_trm,
|
||||
title = {ARM946E-S Technical Reference Manual r1p1},
|
||||
year = 2007,
|
||||
month = apr,
|
||||
organization = {ARM Limited},
|
||||
eid = {ARM DDI 0201D},
|
||||
edition = {Revision D},
|
||||
url = {https://developer.arm.com/documentation/ddi0201/d}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user