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1a15c4b20e
The Xeon Phi x200 family of processors (Knights Landing) supports AVX512 (F, CD, ER, PF) but does not support AVX512 (VL, DQ, BW). Because of processors like this, the Intel Software Developer's Manual suggests the bits AVX512 (DQ,BW,VL) are also tested in EBX together with AVX512F before deciding to run AVX512 (DQ,BW,VL) instructions. This also adds a new x86 feature called avx512_common that indicates that AVX512 (F,DQ,BW,VL) are all available and start using this for both adler32_avx512 and crc32_vpclmulqdq implementations because they are both built with -mavx512dq -mavx512bw -mavx512vl. This has been reported downstream as https://bugzilla.redhat.com/show_bug.cgi?id=2280347 .
101 lines
3.1 KiB
C++
101 lines
3.1 KiB
C++
/* benchmark_adler32.cc -- benchmark adler32 variants
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* Copyright (C) 2022 Nathan Moinvaziri, Adam Stylinski
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* For conditions of distribution and use, see copyright notice in zlib.h
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*/
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#include <stdio.h>
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#include <assert.h>
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#include <benchmark/benchmark.h>
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extern "C" {
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# include "zbuild.h"
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# include "zutil_p.h"
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# include "arch_functions.h"
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# include "../test_cpu_features.h"
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}
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#define MAX_RANDOM_INTS (1024 * 1024)
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#define MAX_RANDOM_INTS_SIZE (MAX_RANDOM_INTS * sizeof(uint32_t))
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class adler32: public benchmark::Fixture {
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private:
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uint32_t *random_ints;
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public:
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void SetUp(const ::benchmark::State& state) {
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/* Control the alignment so that we have the best case scenario for loads. With
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* AVX512, unaligned loads can mean we're crossing a cacheline boundary at every load.
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* And while this is a realistic scenario, it makes it difficult to compare benchmark
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* to benchmark because one allocation could have been aligned perfectly for the loads
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* while the subsequent one happened to not be. This is not to be advantageous to AVX512
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* (indeed, all lesser SIMD implementations benefit from this aligned allocation), but to
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* control the _consistency_ of the results */
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random_ints = (uint32_t *)zng_alloc(MAX_RANDOM_INTS_SIZE);
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assert(random_ints != NULL);
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for (int32_t i = 0; i < MAX_RANDOM_INTS; i++) {
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random_ints[i] = rand();
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}
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}
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void Bench(benchmark::State& state, adler32_func adler32) {
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uint32_t hash = 0;
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for (auto _ : state) {
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hash = adler32(hash, (const unsigned char *)random_ints, (size_t)state.range(0));
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}
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benchmark::DoNotOptimize(hash);
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}
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void TearDown(const ::benchmark::State& state) {
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zng_free(random_ints);
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}
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};
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#define BENCHMARK_ADLER32(name, fptr, support_flag) \
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BENCHMARK_DEFINE_F(adler32, name)(benchmark::State& state) { \
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if (!support_flag) { \
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state.SkipWithError("CPU does not support " #name); \
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} \
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Bench(state, fptr); \
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} \
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BENCHMARK_REGISTER_F(adler32, name)->Arg(1)->Arg(8)->Arg(12)->Arg(16)->Arg(32)->Arg(64)->Arg(512)->Arg(4<<10)->Arg(32<<10)->Arg(256<<10)->Arg(4096<<10)
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BENCHMARK_ADLER32(c, adler32_c, 1);
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#ifdef DISABLE_RUNTIME_CPU_DETECTION
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BENCHMARK_ADLER32(native, native_adler32, 1);
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#else
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#ifdef ARM_NEON
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BENCHMARK_ADLER32(neon, adler32_neon, test_cpu_features.arm.has_neon);
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#endif
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#ifdef PPC_VMX
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BENCHMARK_ADLER32(vmx, adler32_vmx, test_cpu_features.power.has_altivec);
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#endif
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#ifdef POWER8_VSX
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BENCHMARK_ADLER32(power8, adler32_power8, test_cpu_features.power.has_arch_2_07);
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#endif
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#ifdef RISCV_RVV
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BENCHMARK_ADLER32(rvv, adler32_rvv, test_cpu_features.riscv.has_rvv);
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#endif
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#ifdef X86_SSSE3
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BENCHMARK_ADLER32(ssse3, adler32_ssse3, test_cpu_features.x86.has_ssse3);
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#endif
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#ifdef X86_AVX2
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BENCHMARK_ADLER32(avx2, adler32_avx2, test_cpu_features.x86.has_avx2);
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#endif
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#ifdef X86_AVX512
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BENCHMARK_ADLER32(avx512, adler32_avx512, test_cpu_features.x86.has_avx512_common);
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#endif
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#ifdef X86_AVX512VNNI
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BENCHMARK_ADLER32(avx512_vnni, adler32_avx512_vnni, test_cpu_features.x86.has_avx512vnni);
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#endif
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#endif
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