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https://github.com/GerbilSoft/zlib-ng.git
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46fc33f39d
This is ~25-30% faster than the SSE2 variant on a core2 quad. The main reason for this has to do with the fact that, while incurring far fewer shifts, an entirely separate stack buffer has to be managed that is the size of the L1 cache on most CPUs. This was one of the main reasons the 32k specialized function was slower for the scalar counterpart, despite auto vectorizing. The auto vectorized loop was setting up the stack buffer at unaligned offsets, which is detrimental to performance pre-nehalem. Additionally, we were losing a fair bit of time to the zero initialization, which we are now doing more selectively. There are a ton of loads and stores happening, and for sure we are bound on the fill buffer + store forwarding. An SSE2 version of this code is probably possible by simply replacing the shifts with unpacks with zero and the palignr's with shufpd's. I'm just not sure it'll be all that worth it, though. We are gating against SSE4.1 not because we are using specifically a 4.1 instruction but because that marks when Wolfdale came out and palignr became a lot faster.
129 lines
4.0 KiB
C
129 lines
4.0 KiB
C
/* x86_features.c - x86 feature check
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*
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* Copyright (C) 2013 Intel Corporation. All rights reserved.
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* Author:
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* Jim Kukunas
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*
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* For conditions of distribution and use, see copyright notice in zlib.h
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*/
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#include "zbuild.h"
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#include "x86_features.h"
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#if defined(HAVE_CPUID_MS)
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# include <intrin.h>
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#elif defined(HAVE_CPUID_GNU)
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// Newer versions of GCC and clang come with cpuid.h
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# include <cpuid.h>
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# ifdef X86_HAVE_XSAVE_INTRIN
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# if __GNUC__ == 8
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# include <xsaveintrin.h>
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# else
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# include <immintrin.h>
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# endif
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# endif
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#endif
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#include <string.h>
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static inline void cpuid(int info, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#if defined(HAVE_CPUID_MS)
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unsigned int registers[4];
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__cpuid((int *)registers, info);
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*eax = registers[0];
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*ebx = registers[1];
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*ecx = registers[2];
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*edx = registers[3];
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#elif defined(HAVE_CPUID_GNU)
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*eax = *ebx = *ecx = *edx = 0;
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__cpuid(info, *eax, *ebx, *ecx, *edx);
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#else
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/* When using this fallback, the faster SSE/AVX code is disabled */
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*eax = *ebx = *ecx = *edx = 0;
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#endif
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}
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static inline void cpuidex(int info, int subinfo, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#if defined(HAVE_CPUID_MS)
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unsigned int registers[4];
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__cpuidex((int *)registers, info, subinfo);
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*eax = registers[0];
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*ebx = registers[1];
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*ecx = registers[2];
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*edx = registers[3];
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#elif defined(HAVE_CPUID_GNU)
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*eax = *ebx = *ecx = *edx = 0;
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__cpuid_count(info, subinfo, *eax, *ebx, *ecx, *edx);
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#else
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/* When using this fallback, the faster SSE/AVX code is disabled */
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*eax = *ebx = *ecx = *edx = 0;
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#endif
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}
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static inline uint64_t xgetbv(unsigned int xcr) {
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#if defined(_MSC_VER) || defined(X86_HAVE_XSAVE_INTRIN)
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return _xgetbv(xcr);
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#elif defined(__GNUC__)
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uint32_t eax, edx;
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__asm__ ( ".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
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return (uint64_t)(edx) << 32 | eax;
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#else
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/* When using this fallback, some of the faster code is disabled */
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return 0;
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#endif
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}
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void Z_INTERNAL x86_check_features(struct x86_cpu_features *features) {
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unsigned eax, ebx, ecx, edx;
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unsigned maxbasic;
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cpuid(0, &maxbasic, &ebx, &ecx, &edx);
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cpuid(1 /*CPU_PROCINFO_AND_FEATUREBITS*/, &eax, &ebx, &ecx, &edx);
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features->has_sse2 = edx & 0x4000000;
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features->has_ssse3 = ecx & 0x200;
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features->has_sse41 = ecx & 0x80000;
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features->has_sse42 = ecx & 0x100000;
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features->has_pclmulqdq = ecx & 0x2;
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if (ecx & 0x08000000) {
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uint64_t xfeature = xgetbv(0);
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features->has_os_save_ymm = ((xfeature & 0x06) == 0x06);
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features->has_os_save_zmm = ((xfeature & 0xe6) == 0xe6);
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}
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if (maxbasic >= 7) {
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cpuidex(7, 0, &eax, &ebx, &ecx, &edx);
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// check BMI1 bit
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// Reference: https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf
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features->has_vpclmulqdq = ecx & 0x400;
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// check AVX2 bit if the OS supports saving YMM registers
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if (features->has_os_save_ymm) {
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features->has_avx2 = ebx & 0x20;
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}
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features->has_bmi2 = ebx & 0x8;
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// check AVX512 bits if the OS supports saving ZMM registers
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if (features->has_os_save_zmm) {
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features->has_avx512f = ebx & 0x00010000;
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if (features->has_avx512f) {
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// According to the Intel Software Developer's Manual, AVX512F must be enabled too in order to enable
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// AVX512(DQ,BW,VL).
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features->has_avx512dq = ebx & 0x00020000;
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features->has_avx512bw = ebx & 0x40000000;
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features->has_avx512vl = ebx & 0x80000000;
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}
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features->has_avx512_common = features->has_avx512f && features->has_avx512dq && features->has_avx512bw \
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&& features->has_avx512vl && features->has_bmi2;
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features->has_avx512vnni = ecx & 0x800;
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}
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}
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}
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