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https://github.com/ApacheThunder/ezfo-disc_io.git
synced 2025-06-18 19:15:33 -04:00
Attempt to refactor on original EZFlash code.
* FPGA or DLDI driver code randomly hanging during tests with nds-sd-benchmark app. This on occasion causes corruption of root direction which causes all files to go missing. Maybe flaw in original EZFlash code? Not sure yet. Currentlyt using tonccpy in place of dmaCopy since one shouldn't use dmaCopy on arm9 for DLDI drivers.
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ApacheThunder
parent
f7b475b913
commit
97d33a0c10
3
.gitignore
vendored
3
.gitignore
vendored
@ -52,4 +52,5 @@ Mkfile.old
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dkms.conf
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# Compiled DLDI files
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*.dldi
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*.dldi
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*.nds
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211
source/io_ezfo.c
211
source/io_ezfo.c
@ -33,11 +33,15 @@
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#define SET_info_offset 0x7B0000
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#define FlashBase_S71 0x08000000
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#define FlashBase_S98 0x09000000
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#define SDBufferAddress 0x09E00000
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#define OMEGA_ROM_UNKNOWN 0x0000
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#define OMEGA_ROM_PSRAM 0x9780
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#define OMEGA_ROM_NOR 0xFFFF
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#define OMEGA_MAGIC1 0xD200
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#define OMEGA_MAGIC2 0x1500
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#define OMEGA_ROM_PAGE_UNKNOWN 0xFFFF
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#define OMEGA_ROM_PAGE_PSRAM 0x0200
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// #define OMEGA_ROM_PAGE_KERNEL 0x8000
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@ -49,6 +53,7 @@
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#define OMEGA_SD_CTL_ENABLE OMEGA_SD_BIT_ENABLE
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#define OMEGA_SD_CTL_READ_STATE (OMEGA_SD_BIT_ENABLE | OMEGA_SD_BIT_READ_STATE)
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#define OMEGA_SD_CTL_DISABLE 0x0
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#define OMEGA_SD_WAIT 0x1388
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/**
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*
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@ -66,41 +71,66 @@ static inline void _Spin( u32 _cycles ) {
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*
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*/
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static inline void _Omega_SetROMPage( const u16 _page ) {
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*(vu16*)0x9fe0000 = 0xd200;
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*(vu16*)0x8000000 = 0x1500;
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*(vu16*)0x8020000 = 0xd200;
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*(vu16*)0x8040000 = 0x1500;
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static inline void _Omega_SetROMPage(const u16 _page) {
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*(vu16*)0x9fe0000 = OMEGA_MAGIC1;
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*(vu16*)FlashBase_S71 = OMEGA_MAGIC2;
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*(vu16*)0x8020000 = OMEGA_MAGIC1;
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*(vu16*)0x8040000 = OMEGA_MAGIC2;
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*(vu16*)0x9880000 = _page;
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*(vu16*)0x9fc0000 = 0x1500;
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*(vu16*)0x9fc0000 = OMEGA_MAGIC2;
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}
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static inline void _Omega_SetSDControl( const u16 _control ) {
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/*static inline void _Omega_SetSDControl( const u16 _control ) {
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*(vu16*)0x9fe0000 = 0xd200;
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*(vu16*)0x8000000 = 0x1500;
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*(vu16*)0x8020000 = 0xd200;
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*(vu16*)0x8040000 = 0x1500;
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*(vu16*)0x9400000 = _control;
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*(vu16*)0x9fc0000 = 0x1500;
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}*/
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u16 Read_S98NOR_ID() {
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*((vu16*)FlashBase_S98) = 0xF0;
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*((vu16*)(FlashBase_S98 + (0x555 * 2))) = 0xAA;
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*((vu16*)(FlashBase_S98 + (0x2AA * 2))) = 0x55;
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*((vu16*)(FlashBase_S98 + (0x555 * 2))) = 0x90;
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return *((vu16*)(FlashBase_S98 + (0xE * 2)));
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}
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static inline u16 Read_S98NOR_ID() {
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*((vu16*)(FlashBase_S98)) = 0xF0;
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*((vu16*)(FlashBase_S98+0x555*2)) = 0xAA;
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*((vu16*)(FlashBase_S98+0x2AA*2)) = 0x55;
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*((vu16*)(FlashBase_S98+0x555*2)) = 0x90;
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return *((vu16*)(FlashBase_S98+0xE*2));
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}
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static inline u32 _Omega_WaitSDResponse() {
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/*static inline u32 _Omega_WaitSDResponse() {
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vu16 response;
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u32 waitSpin = 0;
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while ( waitSpin < 0x100000 ) {
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response = *(vu16* )0x9E00000;
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if ( response != 0xEEE1 )return 0;
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while (waitSpin < 0x100000) {
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response = *(vu16*)0x9E00000;
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if (response != 0xEEE1)return 0;
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waitSpin += 1;
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}
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return 1;
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}*/
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void SetSDControl(u16 control) {
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*(u16*)0x9fe0000 = OMEGA_MAGIC1;
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*(u16*)FlashBase_S71 = OMEGA_MAGIC2;
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*(u16*)0x8020000 = OMEGA_MAGIC1;
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*(u16*)0x8040000 = OMEGA_MAGIC2;
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*(u16*)0x9400000 = control;
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*(u16*)0x9fc0000 = OMEGA_MAGIC2;
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}
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void SD_Enable(void) { SetSDControl(1); }
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void SD_Read_state(void) { SetSDControl(3); }
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void SD_Disable(void) { SetSDControl(0); }
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u16 SD_Response(void) { return *(vu16*)SDBufferAddress; }
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u32 Wait_SD_Response() {
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vu16 res;
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u32 count = 0;
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while(1) {
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res = SD_Response();
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if (res != 0xEEE1)return 0;
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count++;
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if (count > 0x100000)return 1;
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}
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}
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/**
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@ -111,27 +141,65 @@ static inline u32 _Omega_WaitSDResponse() {
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bool _EZFO_startUp() {
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_Omega_SetROMPage(OMEGA_ROM_PAGE_KERNEL);
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_Spin(5000);
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// _Spin(OMEGA_SD_WAIT);
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if (Read_S98NOR_ID() == 0x223D) {
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#ifdef NDS
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_Omega_SetSDControl(OMEGA_SD_CTL_ENABLE);
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#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif
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return true;
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}
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#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif
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return false;
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}
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bool _EZFO_isInserted() { return true; }
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bool _EZFO_readSectors(u32 _address, u32 _count, void* _buffer) {
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bool _EZFO_readSectors(u32 address, u32 count, u8* SDbuffer) {
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SD_Enable();
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#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_KERNEL); // Change to OS mode
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_Omega_SetSDControl(OMEGA_SD_CTL_ENABLE);
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#endif
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u32 readsRemain = 2;
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u16 i;
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u16 blocks;
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u32 res;
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u32 times=2;
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for(i = 0; i < count; i += 4) {
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blocks = (count - i > 4) ? 4: (count - i);
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read_again:
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*(vu16*)0x9fe0000 = OMEGA_MAGIC1;
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*(vu16*)FlashBase_S71 = OMEGA_MAGIC2;
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*(vu16*)0x8020000 = OMEGA_MAGIC1;
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*(vu16*)0x8040000 = OMEGA_MAGIC2;
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*(vu16*)0x9600000 = ((address + i) & 0x0000FFFF);
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*(vu16*)0x9620000 = (((address + i) & 0xFFFF0000) >> 16);
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*(vu16*)0x9640000 = blocks;
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*(vu16*)0x9fc0000 = OMEGA_MAGIC2;
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SD_Read_state();
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res = Wait_SD_Response();
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SD_Enable();
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if(res == 1) {
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times--;
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if(times) {
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_Spin(OMEGA_SD_WAIT);
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goto read_again;
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}
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}
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#ifndef NDS
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dmaCopy((void*)SDBufferAddress, (SDbuffer + i * BYTES_PER_READ), (blocks * BYTES_PER_READ));
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#else
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tonccpy((u8*)(SDbuffer + i * BYTES_PER_READ), (u16*)SDBufferAddress, (blocks * BYTES_PER_READ));
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#endif
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}
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SD_Disable();
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/*u32 readsRemain = 2;
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for (u16 ii = 0; ii < _count; ii += 4) {
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const u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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// const u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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while (readsRemain) {
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*(vu16*)0x9fe0000 = 0xd200;
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@ -139,73 +207,112 @@ bool _EZFO_readSectors(u32 _address, u32 _count, void* _buffer) {
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*(vu16*)0x8020000 = 0xd200;
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*(vu16*)0x8040000 = 0x1500;
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*(vu16*)0x9600000 = ((_address + ii) & 0x0000FFFF);
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*(vu16*)0x9620000 = ((_address + ii) & 0xFFFF0000) >> 16;
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*(vu16*)0x9620000 = (((_address + ii) & 0xFFFF0000) >> 16);
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*(vu16*)0x9640000 = blocks;
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*(vu16*)0x9fc0000 = 0x1500;
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_Omega_SetSDControl(OMEGA_SD_CTL_READ_STATE);
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const u32 response = _Omega_WaitSDResponse();
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// const u32 response = _Omega_WaitSDResponse();
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u32 response = _Omega_WaitSDResponse();
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_Omega_SetSDControl(OMEGA_SD_CTL_ENABLE);
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if (response && --readsRemain) {
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_Spin(5000);
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_Spin(OMEGA_SD_WAIT);
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} else {
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#ifndef NDS
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dmaCopy((void*)0x9E00000, (void*)(_buffer + ii * 512), (blocks * BYTES_PER_READ));
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#ifdef NDS
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tonccpy((u32*)(_buffer + ii * 512), (u16*)0x9E00000, (blocks * BYTES_PER_READ));
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#else
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tonccpy((void*)(_buffer + ii * 512), (void*)0x9E00000, (blocks * BYTES_PER_READ));
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dmaCopy((void*)0x9E00000, (void*)(_buffer + ii * 512), (blocks * BYTES_PER_READ));
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#endif
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break;
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}
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}
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}
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}*/
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SD_Disable();
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#ifndef NDS
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_Omega_SetSDControl(OMEGA_SD_CTL_DISABLE);
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif
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return true;
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}
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bool _EZFO_writeSectors(u32 _address, u32 _count, void* _buffer ) {
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bool _EZFO_writeSectors(u32 address, u16 count, const u8* SDbuffer) {
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#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_KERNEL); // Change to OS mode
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#endif
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#ifdef _IO_USE_DMA
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DC_FlushRange(_buffer, (_count * BYTES_PER_READ));
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SD_Enable();
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SD_Read_state();
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u16 i;
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u16 blocks;
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u32 res;
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for(i = 0; i < count; i += 4) {
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blocks = (count - i > 4) ? 4 : (count - i);
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#ifdef NDS
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tonccpy((u16*)SDBufferAddress, (u8*)(SDbuffer + i * BYTES_PER_READ), (blocks * BYTES_PER_READ));
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#else
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dmaCopy((SDbuffer + i * BYTES_PER_READ), (void*)SDBufferAddress, (blocks * BYTES_PER_READ));
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#endif
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*(vu16*)0x9fe0000 = OMEGA_MAGIC1;
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*(vu16*)FlashBase_S71 = OMEGA_MAGIC2;
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*(vu16*)0x8020000 = OMEGA_MAGIC1;
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*(vu16*)0x8040000 = OMEGA_MAGIC2;
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*(vu16*)0x9600000 = ((address + i) & 0x0000FFFF);
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*(vu16*)0x9620000 = (((address + i) & 0xFFFF0000) >> 16);
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*(vu16*)0x9640000 = (0x8000 + blocks);
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*(vu16*)0x9fc0000 = OMEGA_MAGIC2;
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res = Wait_SD_Response();
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if(res == 1)return false;
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}
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_Spin(0x0BB8);
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SD_Disable();
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#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif
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/*#ifndef NDS
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_Omega_SetROMPage(OMEGA_ROM_PAGE_KERNEL); // Change to OS mode
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_Omega_SetSDControl(OMEGA_SD_CTL_READ_STATE);
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#endif
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// _Omega_SetSDControl(OMEGA_SD_CTL_READ_STATE);
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for (u16 ii = 0; ii < _count; ii++) {
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const u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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#ifndef NDS
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dmaCopy((_buffer + ii * 512), (void*)0x9E00000, (blocks * BYTES_PER_READ));
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// const u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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u16 blocks = (_count - ii > 4) ? 4 : (_count - ii);
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#ifdef NDS
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tonccpy((u16*)0x9E00000, (u32*)(_buffer + ii * 512), (blocks * BYTES_PER_READ));
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#else
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tonccpy((void*)0x9E00000, (_buffer + ii * 512), (blocks * BYTES_PER_READ));
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dmaCopy((void*)(_buffer + ii * 512), (void*)0x9E00000, (blocks * BYTES_PER_READ));
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#endif
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*(vu16*)0x9fe0000 = 0xd200;
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*(vu16*)0x8000000 = 0x1500;
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*(vu16*)0x8020000 = 0xd200;
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*(vu16*)0x8040000 = 0x1500;
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*(vu16*)0x9600000 = ((_address + ii) & 0x0000FFFF);
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*(vu16*)0x9620000 = ((_address + ii) & 0xFFFF0000) >> 16;
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*(vu16*)0x9620000 = (((_address + ii) & 0xFFFF0000) >> 16);
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*(vu16*)0x9640000 = (0x8000 + blocks);
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*(vu16*)0x9fc0000 = 0x1500;
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_Omega_WaitSDResponse();
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if(res==1)
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return 1;
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}
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_Spin(3000);
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// _Spin(3000);
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_Spin(OMEGA_SD_WAIT);
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#ifndef NDS
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_Omega_SetSDControl(OMEGA_SD_CTL_DISABLE);
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif*/
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return true;
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}
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bool _EZFO_clearStatus() { return true; }
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bool _EZFO_shutdown() {
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SD_Disable();
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#ifndef NDS
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// _Omega_SetSDControl(OMEGA_SD_CTL_DISABLE);
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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#endif
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return true;
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}
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bool _EZFO_clearStatus() { return true; }
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bool _EZFO_shutdown() {
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_Omega_SetSDControl(OMEGA_SD_CTL_DISABLE);
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_Omega_SetROMPage(OMEGA_ROM_PAGE_PSRAM); // Return to original mode
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return true;
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}
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