mirror of
https://github.com/ApacheThunder/XuluMenu.git
synced 2025-06-18 19:45:45 -04:00

* Can now boot stage2 (in safe block mode) if holding L-Shoulder + R-Shoulder + A + B + DPAD Up on boot. This allows using built in stage2 usb update mode for "bootleg" style N-Cards that have Xulumenu installed. * This button combo will not do anything for regular N-Card users as they already have a proper stage2 section on nand and it will always end up booting to USB update mode with this button combo before xulumenu can boot.
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
/*
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main.arm7.c
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By Michael Chisholm (Chishm)
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All resetMemory and startBinary functions are based
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on the MultiNDS loader by Darkain.
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Original source available at:
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http://cvs.sourceforge.net/viewcvs.py/ndslib/ndslib/examples/loader/boot/main.cpp
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License:
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NitroHax -- Cheat tool for the Nintendo DS
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Copyright (C) 2008 Michael "Chishm" Chisholm
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef ARM7
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# define ARM7
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#endif
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#include <nds/ndstypes.h>
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#include <nds/memory.h>
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#include <nds/system.h>
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#include <nds/interrupts.h>
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#include <nds/timers.h>
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#include <nds/dma.h>
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#include <nds/arm7/audio.h>
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#include <nds/ipc.h>
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#include <nds/card.h>
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#ifndef NULL
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#define NULL 0
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#endif
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#include "common.h"
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#include "tonccpy.h"
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extern void arm7_clearmem (void* loc, size_t len);
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extern void arm7_reset (void);
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#define NDS_HEADER 0x02FFFE00
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#define TMP_DATA 0x02100000
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#define FW_READ 0x03
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tNDSHeader* ndsHeader;
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void arm7_readFirmware (uint32 address, uint8 * buffer, uint32 size) {
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uint32 index;
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// Read command
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while (REG_SPICNT & SPI_BUSY);
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REG_SPICNT = SPI_ENABLE | SPI_CONTINUOUS | SPI_DEVICE_NVRAM;
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REG_SPIDATA = FW_READ;
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while (REG_SPICNT & SPI_BUSY);
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// Set the address
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REG_SPIDATA = (address>>16) & 0xFF;
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while (REG_SPICNT & SPI_BUSY);
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REG_SPIDATA = (address>>8) & 0xFF;
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while (REG_SPICNT & SPI_BUSY);
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REG_SPIDATA = (address) & 0xFF;
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while (REG_SPICNT & SPI_BUSY);
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for (index = 0; index < size; index++) {
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REG_SPIDATA = 0;
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while (REG_SPICNT & SPI_BUSY);
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buffer[index] = REG_SPIDATA & 0xFF;
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}
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REG_SPICNT = 0;
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}
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void arm7_resetMemory () {
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int i;
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u8 settings1, settings2;
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REG_IME = 0;
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for (i=0; i<16; i++) {
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SCHANNEL_CR(i) = 0;
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SCHANNEL_TIMER(i) = 0;
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SCHANNEL_SOURCE(i) = 0;
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SCHANNEL_LENGTH(i) = 0;
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}
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REG_SOUNDCNT = 0;
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// Clear out ARM7 DMA channels and timers
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for (i=0; i<4; i++) {
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DMA_CR(i) = 0;
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DMA_SRC(i) = 0;
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DMA_DEST(i) = 0;
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TIMER_CR(i) = 0;
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TIMER_DATA(i) = 0;
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}
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// Clear out FIFO
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REG_IPC_SYNC = 0;
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REG_IPC_FIFO_CR = IPC_FIFO_ENABLE | IPC_FIFO_SEND_CLEAR;
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REG_IPC_FIFO_CR = 0;
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// clear IWRAM - 037F:8000 to 0380:FFFF, total 96KiB
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arm7_clearmem ((void*)0x037F8000, 96*1024);
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// clear last part of EXRAM, skipping the ARM9's section
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arm7_clearmem ((void*)0x023FE000, 0x2000);
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// clear most of EXRAM - except after 0x023FD800, which has the ARM9 code
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// arm7_clearmem ((void*)0x02000000, 0x003FD800);
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arm7_clearmem ((void*)0x02000000, 0x000FFFFF); // Skip temperary header/binary data
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REG_IE = 0;
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REG_IF = ~0;
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(*(vu32*)(0x04000000-4)) = 0; //IRQ_HANDLER ARM7 version
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(*(vu32*)(0x04000000-8)) = ~0; //VBLANK_INTR_WAIT_FLAGS, ARM7 version
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REG_POWERCNT = 1; //turn off power to stuffs
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// Reload DS Firmware settings
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arm7_readFirmware((u32)0x03FE70, &settings1, 0x1);
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arm7_readFirmware((u32)0x03FF70, &settings2, 0x1);
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if (settings1 > settings2) {
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arm7_readFirmware((u32)0x03FE00, (u8*)0x027FFC80, 0x70);
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arm7_readFirmware((u32)0x03FF00, (u8*)0x027FFD80, 0x70);
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} else {
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arm7_readFirmware((u32)0x03FF00, (u8*)0x027FFC80, 0x70);
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arm7_readFirmware((u32)0x03FE00, (u8*)0x027FFD80, 0x70);
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}
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// Load FW header
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arm7_readFirmware((u32)0x000000, (u8*)0x027FF830, 0x20);
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}
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void arm7_loadBinary() {
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tonccpy((void*)NDS_HEADER, (void*)TMP_DATA, 0x160);
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ndsHeader = (tNDSHeader*)NDS_HEADER;
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// Copy arm binaries and header to intended locations.
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tonccpy((void*)ndsHeader->arm9destination, ((void*)((u32)TMP_DATA + ndsHeader->arm9romOffset)), ndsHeader->arm9binarySize);
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tonccpy((void*)ndsHeader->arm7destination, ((void*)((u32)TMP_DATA + ndsHeader->arm7romOffset)), ndsHeader->arm7binarySize);
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// Clear temperary rom data now that they are copied
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arm7_clearmem ((void*)0x02100000, ndsHeader->romSize);
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}
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//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// Main function
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void arm7_main (void) {
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// Synchronise start
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while (ipcRecvState() != ARM9_START);
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ipcSendState(ARM7_START);
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// Wait until ARM9 is ready
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while (ipcRecvState() != ARM9_READY);
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ipcSendState(ARM7_MEMCLR);
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// Get ARM7 to clear RAM
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arm7_resetMemory();
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ipcSendState(ARM7_LOADBIN);
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arm7_loadBinary();
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ipcSendState(ARM7_BOOTBIN);
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arm7_reset();
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}
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