mirror of
https://github.com/ApacheThunder/XuluMenu.git
synced 2025-06-19 03:55:32 -04:00
2550af0c99
* Can now boot stage2 (in safe block mode) if holding L-Shoulder + R-Shoulder + A + B + DPAD Up on boot. This allows using built in stage2 usb update mode for "bootleg" style N-Cards that have Xulumenu installed. * This button combo will not do anything for regular N-Card users as they already have a proper stage2 section on nand and it will always end up booting to USB update mode with this button combo before xulumenu can boot.
135 lines
3.9 KiB
ArmAsm
135 lines
3.9 KiB
ArmAsm
/*
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Copyright 2006 - 2015 Dave Murphy (WinterMute)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nds/arm9/cache_asm.h>
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.text
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.align 4
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.arm
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.arch armv5te
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.cpu arm946e-s
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@---------------------------------------------------------------------------------
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.global arm9_reset
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.type arm9_reset STT_FUNC
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@---------------------------------------------------------------------------------
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arm9_reset:
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@---------------------------------------------------------------------------------
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mrs r0, cpsr @ cpu interrupt disable
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orr r0, r0, #0x80 @ (set i flag)
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msr cpsr, r0
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@ Switch off MPU
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #PROTECT_ENABLE
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mcr p15, 0, r0, c1, c0, 0
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adr r12, mpu_initial_data
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ldmia r12, {r0-r10}
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r0, c2, c0, 1
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mcr p15, 0, r1, c3, c0, 0
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mcr p15, 0, r2, c5, c0, 2
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mcr p15, 0, r3, c5, c0, 3
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mcr p15, 0, r4, c6, c0, 0
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mcr p15, 0, r5, c6, c1, 0
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mcr p15, 0, r6, c6, c3, 0
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mcr p15, 0, r7, c6, c4, 0
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mcr p15, 0, r8, c6, c6, 0
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mcr p15, 0, r9, c6, c7, 0
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mcr p15, 0, r10, c9, c1, 0
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mov r0, #0
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mcr p15, 0, r0, c6, c2, 0 @ PU Protection Unit Data/Unified Region 2
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mcr p15, 0, r0, c6, c5, 0 @ PU Protection Unit Data/Unified Region 5
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mrc p15, 0, r0, c9, c1, 0 @ DTCM
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mov r0, r0, lsr #12 @ base
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mov r0, r0, lsl #12 @ size
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add r0, r0, #0x4000 @ dtcm top
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sub r0, r0, #4 @ irq vector
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mov r1, #0
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str r1, [r0]
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sub r0, r0, #4 @ IRQ1 Check Bits
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str r1, [r0]
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bic r0, r0, #0x7f
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msr cpsr_c, #0xd3 @ svc mode
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mov sp, r0
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sub r0, r0, #64
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msr cpsr_c, #0xd2 @ irq mode
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mov sp, r0
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sub r0, r0, #4096
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msr cpsr_c, #0xdf @ system mode
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mov sp, r0
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mov r12, #0x04000000
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add r12, r12, #0x180
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@ ipcSendState(ARM9_RESET)
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mov r0, #0x200
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strh r0, [r12]
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@ while (ipcRecvState() != ARM7_RESET);
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mov r0, #2
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bl waitsync
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@ ipcSendState(ARM9_BOOT)
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mov r0, #0
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strh r0, [r12]
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@ while (ipcRecvState() != ARM7_BOOT);
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bl waitsync
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ldr r10, =0x2FFFE24
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ldr r2, [r10]
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@ Switch MPU to startup default
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ldr r0, =0x00012078
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mcr p15, 0, r0, c1, c0, 0
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bx r2
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.pool
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@---------------------------------------------------------------------------------
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waitsync:
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@---------------------------------------------------------------------------------
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ldrh r1, [r12]
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and r1, r1, #0x000f
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cmp r0, r1
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bne waitsync
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bx lr
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mpu_initial_data:
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.word 0x00000042 @ p15,0,c2,c0,0..1,r0 ;PU Cachability Bits for Data/Unified+Instruction Protection Region
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.word 0x00000002 @ p15,0,c3,c0,0,r1 ;PU Write-Bufferability Bits for Data Protection Regions
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.word 0x15111011 @ p15,0,c5,c0,2,r2 ;PU Extended Access Permission Data/Unified Protection Region
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.word 0x05100011 @ p15,0,c5,c0,3,r3 ;PU Extended Access Permission Instruction Protection Region
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.word 0x04000033 @ p15,0,c6,c0,0,r4 ;PU Protection Unit Data/Unified Region 0
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.word 0x0200002b @ p15,0,c6,c1,0,r5 ;PU Protection Unit Data/Unified Region 1 4MB
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.word 0x08000035 @ p15,0,c6,c3,0,r6 ;PU Protection Unit Data/Unified Region 3
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.word 0x0300001b @ p15,0,c6,c4,0,r7 ;PU Protection Unit Data/Unified Region 4
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.word 0xffff001d @ p15,0,c6,c6,0,r8 ;PU Protection Unit Data/Unified Region 6
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.word 0x02fff017 @ p15,0,c6,c7,0,r9 ;PU Protection Unit Data/Unified Region 7 4KB
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.word 0x0300000a @ p15,0,c9,c1,0,r10 ;TCM Data TCM Base and Virtual Size
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itcm_reset_code_end: |