mirror of
https://github.com/ApacheThunder/XuluMenu.git
synced 2025-06-19 03:55:32 -04:00
2550af0c99
* Can now boot stage2 (in safe block mode) if holding L-Shoulder + R-Shoulder + A + B + DPAD Up on boot. This allows using built in stage2 usb update mode for "bootleg" style N-Cards that have Xulumenu installed. * This button combo will not do anything for regular N-Card users as they already have a proper stage2 section on nand and it will always end up booting to USB update mode with this button combo before xulumenu can boot.
82 lines
2.0 KiB
ArmAsm
82 lines
2.0 KiB
ArmAsm
/*
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Copyright 2015 Dave Murphy (WinterMute)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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.text
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.align 4
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.arm
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@---------------------------------------------------------------------------------
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.global arm7_reset
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.type arm7_reset STT_FUNC
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@---------------------------------------------------------------------------------
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arm7_reset:
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@---------------------------------------------------------------------------------
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mrs r0, cpsr @ cpu interrupt disable
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orr r0, r0, #0x80 @ (set i flag)
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msr cpsr, r0
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ldr r0, =0x380FFFC @ irq vector
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mov r1, #0
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str r1, [r0]
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sub r0, r0, #4 @ IRQ1 Check Bits
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str r1, [r0]
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sub r0, r0, #4 @ IRQ2 Check Bits
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str r1, [r0]
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bic r0, r0, #0x7f
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msr cpsr_c, #0xd3 @ svc mode
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mov sp, r0
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sub r0, r0, #64
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msr cpsr_c, #0xd2 @ irq mode
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mov sp, r0
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sub r0, r0, #512
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msr cpsr_c, #0xdf @ system mode
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mov sp, r0
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mov r12, #0x04000000
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add r12, r12, #0x180
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@ while (ipcRecvState() != ARM9_RESET);
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mov r0, #2
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bl waitsync
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@ ipcSendState(ARM7_RESET)
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mov r0, #0x200
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strh r0, [r12]
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@ while(ipcRecvState() != ARM9_BOOT);
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mov r0, #0
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bl waitsync
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@ ipcSendState(ARM7_BOOT)
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strh r0, [r12]
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ldr r0,=0x2FFFE34
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ldr r0,[r0]
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bx r0
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.pool
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@---------------------------------------------------------------------------------
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waitsync:
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@---------------------------------------------------------------------------------
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ldrh r1, [r12]
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and r1, r1, #0x000f
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cmp r0, r1
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bne waitsync
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bx lr
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