mirror of
https://github.com/ApacheThunder/NTR_Launcher.git
synced 2025-06-18 19:15:40 -04:00
1e2dfed554
This is the version 1.9.6 build rebased from Chishm's official github of NitroHax which is the project this is based off of.
246 lines
6.4 KiB
C
Executable File
246 lines
6.4 KiB
C
Executable File
/*
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main.arm9.c
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By Michael Chisholm (Chishm)
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All resetMemory and startBinary functions are based
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on the MultiNDS loader by Darkain.
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Original source available at:
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http://cvs.sourceforge.net/viewcvs.py/ndslib/ndslib/examples/loader/boot/main.cpp
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License:
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NitroHax -- Cheat tool for the Nintendo DS
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Copyright (C) 2008 Michael "Chishm" Chisholm
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define ARM9
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#undef ARM7
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#include <nds/memory.h>
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#include <nds/arm9/video.h>
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#include <nds/arm9/input.h>
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#include <nds/interrupts.h>
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#include <nds/dma.h>
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#include <nds/timers.h>
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#include <nds/system.h>
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#include <nds/ipc.h>
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#include "common.h"
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volatile int arm9_stateFlag = ARM9_BOOT;
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volatile u32 arm9_errorCode = 0xFFFFFFFF;
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volatile bool arm9_errorClearBG = false;
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volatile u32 arm9_BLANK_RAM = 0;
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/*-------------------------------------------------------------------------
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External functions
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--------------------------------------------------------------------------*/
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extern void arm9_clearCache (void);
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/*-------------------------------------------------------------------------
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arm9_errorOutput
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Displays an error code on screen.
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Written by Chishm
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--------------------------------------------------------------------------*/
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/* Re-enable for debug purposes
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static void arm9_errorOutput (u32 code, bool clearBG) {
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int i, j, k;
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u16 colour;
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REG_POWERCNT = POWER_LCD | POWER_2D_A;
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REG_DISPCNT = MODE_FB0;
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VRAM_A_CR = VRAM_ENABLE;
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if (clearBG) {
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// Clear display
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for (i = 0; i < 256*192; i++) {
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VRAM_A[i] = 0x0000;
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}
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}
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// Draw boxes of colour, signifying error codes
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if ((code >> 16) != 0) {
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// high 16 bits
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for (i = 0; i < 8; i++) { // Pair of bits to use
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if (((code>>(30-2*i))&3) == 0) {
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colour = 0x001F; // Red
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} else if (((code>>(30-2*i))&3) == 1) {
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colour = 0x03FF; // Yellow
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} else if (((code>>(30-2*i))&3) == 2) {
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colour = 0x03E0; // Green
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} else {
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colour = 0x7C00; // Blue
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}
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for (j = 71; j < 87; j++) { // Row
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for (k = 32*i+8; k < 32*i+24; k++) { // Column
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VRAM_A[j*256+k] = colour;
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}
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}
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}
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}
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if ((code >> 8) != 0) {
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// Low 16 bits
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for (i = 0; i < 8; i++) { // Pair of bits to use
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if (((code>>(14-2*i))&3) == 0) {
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colour = 0x001F; // Red
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} else if (((code>>(14-2*i))&3) == 1) {
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colour = 0x03FF; // Yellow
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} else if (((code>>(14-2*i))&3) == 2) {
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colour = 0x03E0; // Green
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} else {
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colour = 0x7C00; // Blue
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}
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for (j = 103; j < 119; j++) { // Row
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for (k = 32*i+8; k < 32*i+24; k++) { // Column
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VRAM_A[j*256+k] = colour;
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}
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}
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}
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} else {
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// Low 8 bits
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for (i = 0; i < 4; i++) { // Pair of bits to use
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if (((code>>(6-2*i))&3) == 0) {
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colour = 0x001F; // Red
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} else if (((code>>(6-2*i))&3) == 1) {
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colour = 0x03FF; // Yellow
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} else if (((code>>(6-2*i))&3) == 2) {
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colour = 0x03E0; // Green
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} else {
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colour = 0x7C00; // Blue
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}
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for (j = 87; j < 103; j++) { // Row
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for (k = 32*i+72; k < 32*i+88; k++) { // Column
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VRAM_A[j*256+k] = colour;
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}
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}
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}
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}
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}
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*/
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/*-------------------------------------------------------------------------
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arm9_main
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Clears the ARM9's icahce and dcache
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Clears the ARM9's DMA channels and resets video memory
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Jumps to the ARM9 NDS binary in sync with the display and ARM7
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Written by Darkain, modified by Chishm
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--------------------------------------------------------------------------*/
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void arm9_main (void) {
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// volatile u32* SCFG_EXT = (volatile u32*)0x4004008;
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// volatile u32* SCFG_CLK = (volatile u32*)0x4004004;
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register int i;
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//set shared ram to ARM7
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WRAM_CR = 0x03;
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REG_EXMEMCNT = 0xE880;
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arm9_stateFlag = ARM9_START;
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REG_IME = 0;
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REG_IE = 0;
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REG_IF = ~0;
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arm9_clearCache();
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for (i=0; i<16*1024; i+=4) { //first 16KB
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(*(vu32*)(i+0x00000000)) = 0x00000000; //clear ITCM
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(*(vu32*)(i+0x00800000)) = 0x00000000; //clear DTCM
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}
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for (i=16*1024; i<32*1024; i+=4) { //second 16KB
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(*(vu32*)(i+0x00000000)) = 0x00000000; //clear ITCM
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}
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arm9_stateFlag = ARM9_MEMCLR;
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(*(vu32*)0x00803FFC) = 0; //IRQ_HANDLER ARM9 version
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(*(vu32*)0x00803FF8) = ~0; //VBLANK_INTR_WAIT_FLAGS ARM9 version
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//clear out ARM9 DMA channels
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for (i=0; i<4; i++) {
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DMA_CR(i) = 0;
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DMA_SRC(i) = 0;
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DMA_DEST(i) = 0;
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TIMER_CR(i) = 0;
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TIMER_DATA(i) = 0;
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}
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// Clear out FIFO
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REG_IPC_SYNC = 0;
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REG_IPC_FIFO_CR = IPC_FIFO_ENABLE | IPC_FIFO_SEND_CLEAR;
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REG_IPC_FIFO_CR = 0;
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VRAM_A_CR = 0x80;
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VRAM_B_CR = 0x80;
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// Don't mess with the VRAM used for execution
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// VRAM_C_CR = 0;
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VRAM_D_CR = 0x80;
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VRAM_E_CR = 0x80;
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VRAM_F_CR = 0x80;
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VRAM_G_CR = 0x80;
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VRAM_H_CR = 0x80;
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VRAM_I_CR = 0x80;
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BG_PALETTE[0] = 0xFFFF;
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dmaFill((void*)&arm9_BLANK_RAM, BG_PALETTE+1, (2*1024)-2);
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dmaFill((void*)&arm9_BLANK_RAM, OAM, 2*1024);
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dmaFill((void*)&arm9_BLANK_RAM, (void*)0x04000000, 0x56); //clear main display registers
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dmaFill((void*)&arm9_BLANK_RAM, (void*)0x04001000, 0x56); //clear sub display registers
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dmaFill((void*)&arm9_BLANK_RAM, VRAM_A, 256*1024); // Banks A, B
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dmaFill((void*)&arm9_BLANK_RAM, VRAM_D, 272*1024); // Banks D, E, F, G, H, I
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REG_DISPSTAT = 0;
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videoSetMode(0);
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videoSetModeSub(0);
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VRAM_A_CR = 0;
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VRAM_B_CR = 0;
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// Don't mess with the VRAM used for execution
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// VRAM_C_CR = 0;
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VRAM_D_CR = 0;
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VRAM_E_CR = 0;
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VRAM_F_CR = 0;
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VRAM_G_CR = 0;
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VRAM_H_CR = 0;
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VRAM_I_CR = 0;
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REG_POWERCNT = 0x820F;
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// set ARM9 state to ready and wait for it to change again
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arm9_stateFlag = ARM9_READY;
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while ( arm9_stateFlag != ARM9_BOOTBIN ) {
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if (arm9_stateFlag == ARM9_DISPERR) {
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// arm9_errorOutput (arm9_errorCode, arm9_errorClearBG);
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if ( arm9_stateFlag == ARM9_DISPERR) {
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arm9_stateFlag = ARM9_READY;
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}
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}
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}
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// wait for vblank then boot
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while(REG_VCOUNT!=191);
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while(REG_VCOUNT==191);
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u32 first = *(u32*)(0x27FFE34);
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// arm9_errorOutput (*(u32*)(first), true);
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void (*newReset)() = *(u32*)(0x27FFE24);
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newReset();
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}
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