mirror of
https://github.com/ApacheThunder/NTR_Launcher.git
synced 2025-06-19 03:25:38 -04:00
33b091861b
Overhaul of old cart loading code courtasy of Robz8. There is however a small regression. This build currently can't boot DS-Xtreme. If you have issues with flashcarts not booting games/homebrew correctly, disable the extended ram option in the ini file. Currently off by default. But it must be on for TWL carts to boot correctly.
63 lines
1.7 KiB
ArmAsm
Executable File
63 lines
1.7 KiB
ArmAsm
Executable File
@---------------------------------------------------------------------------------
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.global _arm9_start
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@---------------------------------------------------------------------------------
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.align 4
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.arm
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@---------------------------------------------------------------------------------
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_arm9_start:
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@---------------------------------------------------------------------------------
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mov r0, #0x04000000 @ IME = 0;
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add r0, r0, #0x208
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strh r0, [r0]
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mov r0, #0x12 @ Switch to IRQ Mode
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msr cpsr, r0
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ldr sp, =__arm9_sp_irq @ Set IRQ stack
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mov r0, #0x13 @ Switch to SVC Mode
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msr cpsr, r0
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ldr sp, =__arm9_sp_svc @ Set SVC stack
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mov r0, #0x1F @ Switch to System Mode
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msr cpsr, r0
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ldr sp, =__arm9_sp_usr @ Set user stack
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ldr r0, =__arm9_bss_start @ Clear BSS section to 0x00
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ldr r1, =__arm9_bss_end
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sub r1, r1, r0
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bl ClearMem
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mov r0, #0 @ int argc
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mov r1, #0 @ char *argv[]
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ldr r3, =arm9_main
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bl _blx_r3_stub @ jump to user code
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@ If the user ever returns, restart
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b _arm9_start
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@---------------------------------------------------------------------------------
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_blx_r3_stub:
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@---------------------------------------------------------------------------------
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bx r3
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@---------------------------------------------------------------------------------
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@ Clear memory to 0x00 if length != 0
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@ r0 = Start Address
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@ r1 = Length
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@---------------------------------------------------------------------------------
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ClearMem:
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@---------------------------------------------------------------------------------
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mov r2, #3 @ Round down to nearest word boundary
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add r1, r1, r2 @ Shouldn't be needed
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bics r1, r1, r2 @ Clear 2 LSB (and set Z)
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bxeq lr @ Quit if copy size is 0
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mov r2, #0
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ClrLoop:
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stmia r0!, {r2}
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subs r1, r1, #4
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bne ClrLoop
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bx lr
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