Updates for better stability™

Removed some features that would see little use like the TWL mode option
and the enable SD option. MBK init code moved and always used. Sets MBK
to proper values for NTR mode (as documented in No$GBA).

Since this build is now intended to be launched from a patched DSi
System Menu, the touch screen mode change code has been removed and and
this no longer requires a custom libnds build that isn't really
available anywhere right now. :P

BootLoader/source/clear_cache.arm9.s

@@ -0,0 +1,68 @@
+@   NitroHax -- Cheat tool for the Nintendo DS
+@   Copyright (C) 2008  Michael "Chishm" Chisholm
+@
+@   This program is free software: you can redistribute it and/or modify
+@   it under the terms of the GNU General Public License as published by
+@   the Free Software Foundation, either version 3 of the License, or
+@   (at your option) any later version.
+@
+@   This program is distributed in the hope that it will be useful,
+@   but WITHOUT ANY WARRANTY; without even the implied warranty of
+@   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+@   GNU General Public License for more details.
+@
+@   You should have received a copy of the GNU General Public License
+@   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+@ Clears ICache and Dcache, and resets the protection units
+@ Originally written by Darkain, modified by Chishm
+
+#include <nds/asminc.h>
+
+.arm
+
+BEGIN_ASM_FUNC arm9_clearCache
+	@ Clean and flush cache
+	mov r1, #0                   
+	outer_loop:                  
+		mov r0, #0                  
+		inner_loop:                 
+			orr r2, r1, r0             
+			mcr p15, 0, r2, c7, c14, 2 
+			add r0, r0, #0x20          
+			cmp r0, #0x400             
+		bne inner_loop              
+		add r1, r1, #0x40000000     
+		cmp r1, #0x0                
+	bne outer_loop               
+
+	mov r3, #0                  
+	mcr p15, 0, r3, c7, c5, 0		@ Flush ICache
+	mcr p15, 0, r3, c7, c6, 0		@ Flush DCache
+	mcr p15, 0, r3, c7, c10, 4		@ empty write buffer
+
+	mcr p15, 0, r3, c3, c0, 0		@ disable write buffer       (def = 0)
+
+	mcr p15, 0, r3, c2, c0, 0		@ disable DTCM and protection unit
+
+	mcr p15, 0, r3, c6, c0, 0		@ disable protection unit 0  (def = 0)
+	mcr p15, 0, r3, c6, c1, 0		@ disable protection unit 1  (def = 0)
+	mcr p15, 0, r3, c6, c2, 0 		@ disable protection unit 2  (def = 0)
+	mcr p15, 0, r3, c6, c3, 0		@ disable protection unit 3  (def = 0)
+	mcr p15, 0, r3, c6, c4, 0		@ disable protection unit 4  (def = ?)
+	mcr p15, 0, r3, c6, c5, 0		@ disable protection unit 5  (def = ?)
+	mcr p15, 0, r3, c6, c6, 0		@ disable protection unit 6  (def = ?)
+	mcr p15, 0, r3, c6, c7, 0		@ disable protection unit 7  (def = ?)
+
+	mcr p15, 0, r3, c5, c0, 3		@ IAccess
+	mcr p15, 0, r3, c5, c0, 2		@ DAccess
+
+	mov r3, #0x00800000
+	add r3, r3, #0x00A
+	mcr p15, 0, r3, c9, c1, 0		@ DTCM base  (def = 0x0080000A) ???
+
+	mov r3, #0x0000000C
+	mcr p15, 0, r3, c9, c1, 1		@ ITCM base  (def = 0x0000000C) ???
+
+	bx lr
+

BootLoader/source/main.arm7.c

@@ -228,13 +228,6 @@ void arm7_startBinary (void)
 // Main function
 
 void arm7_main (void) {
-	
-	if(REG_SCFG_ROM == 0x703) {
-		REG_MBK6=0x09403900;
-		REG_MBK7=0x09803940;
-		REG_MBK8=0x09C03980;
-		REG_MBK9=0xFCFFFF0F;
-	}
 
 	int errorCode;
 	

BootLoader/source/main.arm9.c

@@ -50,9 +50,7 @@ volatile u32 arm9_BLANK_RAM = 0;
 /*-------------------------------------------------------------------------
 External functions
 --------------------------------------------------------------------------*/
-// extern void arm9_clearCache (void);
+extern void arm9_clearCache(void);
-// arm9_clearCache (void);
-void arm9_clearMPU (void);
 
 /*-------------------------------------------------------------------------
 arm9_errorOutput
@@ -158,8 +156,7 @@ void arm9_main (void) {
 	REG_IE = 0;
 	REG_IF = ~0;
 
-	// arm9_clearCache();
+	arm9_clearCache();
-	arm9_clearMPU;
 	
 	for (i=0; i<16*1024; i+=4) {  //first 16KB
 		(*(vu32*)(i+0x00000000)) = 0x00000000;      //clear ITCM
@@ -222,17 +219,6 @@ void arm9_main (void) {
 	VRAM_I_CR = 0;
 	REG_POWERCNT  = 0x820F;
 
-	if(REG_SCFG_ROM == 0x3) {
-		*((vu32*)REG_MBK1)=0x8D898581;
-		*((vu32*)REG_MBK2)=0x91898581;
-		*((vu32*)REG_MBK3)=0x91999591;
-		*((vu32*)REG_MBK4)=0x91898581;
-		*((vu32*)REG_MBK5)=0x91999591;
-	
-		REG_MBK6=0x00003000;
-		REG_MBK7=0x00003000;
-		REG_MBK8=0x00003000;
-	}
 	// set ARM9 state to ready and wait for it to change again
 	arm9_stateFlag = ARM9_READY;
 	while ( arm9_stateFlag != ARM9_BOOTBIN ) {
@@ -251,6 +237,7 @@ void arm9_main (void) {
 	
 	// arm9_errorOutput (*(u32*)(first), true);
 
+
 	((void (*)())(*(u32*)(0x27FFE24)))();
 }
 

BootLoader/source/mpu_reset.s

@@ -1,110 +0,0 @@
-/*
-	Copyright 2006 - 2015 Dave Murphy (WinterMute)
-
-	This program is free software: you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation, either version 2 of the License, or
-	(at your option) any later version.
-
-	This program is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-#include <nds/arm9/cache_asm.h>
-
-	.text
-	.align 4
-
-	.arm
-
-	.arch	armv5te
-	.cpu	arm946e-s
-
-@---------------------------------------------------------------------------------
-	.global arm9_clearMPU
-	.type	arm9_clearMPU STT_FUNC
-@---------------------------------------------------------------------------------
-arm9_clearMPU:
-@---------------------------------------------------------------------------------
-	@ Switch off MPU
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #PROTECT_ENABLE
-	mcr	p15, 0, r0, c1, c0, 0
-
-
-	adr	r12, mpu_initial_data
-	ldmia	r12, {r0-r10}
-
-	mcr	p15, 0, r0, c2, c0, 0
-	mcr	p15, 0, r0, c2, c0, 1
-	mcr	p15, 0, r1, c3, c0, 0
-	mcr	p15, 0, r2, c5, c0, 2
-	mcr	p15, 0, r3, c5, c0, 3
-	mcr	p15, 0, r4, c6, c0, 0
-	mcr	p15, 0, r5, c6, c1, 0
-	mcr	p15, 0, r6, c6, c3, 0
-	mcr	p15, 0, r7, c6, c4, 0
-	mcr	p15, 0, r8, c6, c6, 0
-	mcr	p15, 0, r9, c6, c7, 0
-	mcr	p15, 0, r10, c9, c1, 0
-
-	mov	r0, #0
-	mcr	p15, 0, r0, c6, c2, 0   @ PU Protection Unit Data/Unified Region 2
-	mcr	p15, 0, r0, c6, c5, 0   @ PU Protection Unit Data/Unified Region 5
-
-	mrc	p15, 0, r0, c9, c1, 0   @ DTCM
-	mov	r0, r0, lsr #12         @ base
-	mov	r0, r0, lsl #12         @ size
-	add	r0, r0, #0x4000         @ dtcm top
-
-	sub	r0, r0, #4              @ irq vector
-	mov	r1, #0
-	str 	r1, [r0]
-	sub	r0, r0, #4              @ IRQ1 Check Bits
-	str 	r1, [r0]
-
-	sub	r0, r0, #128
-	bic	r0, r0, #7
-
-	msr	cpsr_c, #0xd3      @ svc mode
-	mov	sp, r0
-	sub	r0, r0, #128
-	msr	cpsr_c, #0xd2      @ irq mode
-	mov	sp, r0
-	sub	r0, r0, #128
-	msr	cpsr_c, #0xdf      @ system mode
-	mov	sp, r0
-
-	@ enable cache & tcm
-	mrc	p15, 0, r0, c1, c0, 0
-	ldr	r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE
-	orr	r0,r0,r1
-	mcr	p15, 0, r0, c1, c0, 0
-
-	ldr	r10, =0x2FFFE04
-	ldr	r0, =0xE59FF018
-	str	r0, [r10]
-	add	r1, r10, #0x20
-	str	r10, [r1]
-	bx	r10
-
-	.pool
-
-mpu_initial_data:
-	.word 0x00000042  @ p15,0,c2,c0,0..1,r0 ;PU Cachability Bits for Data/Unified+Instruction Protection Region
-	.word 0x00000002  @ p15,0,c3,c0,0,r1    ;PU Write-Bufferability Bits for Data Protection Regions
-	.word 0x15111011  @ p15,0,c5,c0,2,r2    ;PU Extended Access Permission Data/Unified Protection Region
-	.word 0x05100011  @ p15,0,c5,c0,3,r3    ;PU Extended Access Permission Instruction Protection Region
-	.word 0x04000033  @ p15,0,c6,c0,0,r4    ;PU Protection Unit Data/Unified Region 0
-	.word 0x0200002b  @ p15,0,c6,c1,0,r5    ;PU Protection Unit Data/Unified Region 1 4MB
-	.word 0x08000035  @ p15,0,c6,c3,0,r6    ;PU Protection Unit Data/Unified Region 3
-	.word 0x0300001b  @ p15,0,c6,c4,0,r7    ;PU Protection Unit Data/Unified Region 4
-	.word 0xffff001d  @ p15,0,c6,c6,0,r8    ;PU Protection Unit Data/Unified Region 6
-	.word 0x02fff017  @ p15,0,c6,c7,0,r9    ;PU Protection Unit Data/Unified Region 7 4KB
-	.word 0x0300000a  @ p15,0,c9,c1,0,r10   ;TCM Data TCM Base and Virtual Size

NTR_Launcher.ini

@@ -1,6 +1,3 @@
 [NTRLAUNCHER]
-NTRTOUCH = 1
+RESETSLOT1 = 1
 TWLCLOCK = 0
-TWLMODE = 0
-ENABLESD = 0
-RESETSLOT1 = 1

arm7/source/fifocheck.c

@@ -18,167 +18,21 @@
 
 #include <nds.h>
 
-//---------------------------------------------------------------------------------
-void NDSTouchscreenMode() {
-//---------------------------------------------------------------------------------
-	u8 volLevel;
-	
-	volLevel = 0xA7;
-
-	volLevel += 0x13;
-
-	readTSCReg(0);
-	writeTSCReg(0,0);
-	writeTSCReg(0x3a,0);
-	readTSCReg(0x51);
-	writeTSCReg(3,0);
-	readTSCReg(2);
-	writeTSCReg(0,0);
-	readTSCReg(0x3f);
-	writeTSCReg(0,1);
-	readTSCReg(0x38);
-	readTSCReg(0x2a);
-	readTSCReg(0x2E);
-	writeTSCReg(0,0);
-	writeTSCReg(0x52,0x80);
-	writeTSCReg(0x40,0xC);
-	writeTSCReg(0,1);
-	writeTSCReg(0x24,0xff);
-	writeTSCReg(0x25,0xff);
-	writeTSCReg(0x26,0x7f);
-	writeTSCReg(0x27,0x7f);
-	writeTSCReg(0x28,0x4a);
-	writeTSCReg(0x29,0x4a);
-	writeTSCReg(0x2a,0x10);
-	writeTSCReg(0x2b,0x10);
-	writeTSCReg(0,0);
-	writeTSCReg(0x51,0);
-	writeTSCReg(0,3);
-	readTSCReg(2);
-	writeTSCReg(2,0x98);
-	writeTSCReg(0,1);
-	writeTSCReg(0x23,0);
-	writeTSCReg(0x1f,0x14);
-	writeTSCReg(0x20,0x14);
-	writeTSCReg(0,0);
-	writeTSCReg(0x3f,0);
-	readTSCReg(0x0b);
-	writeTSCReg(0x5,0);
-	writeTSCReg(0xb,0x1);
-	writeTSCReg(0xc,0x2);
-	writeTSCReg(0x12,0x1);
-	writeTSCReg(0x13,0x2);
-	writeTSCReg(0,1);
-	writeTSCReg(0x2E,0x00);
-	writeTSCReg(0,0);
-	writeTSCReg(0x3A,0x60);
-	writeTSCReg(0x01,01);
-	writeTSCReg(0x9,0x66);
-	writeTSCReg(0,1);
-	readTSCReg(0x20);
-	writeTSCReg(0x20,0x10);
-	writeTSCReg(0,0);
-	writeTSCReg( 04,00);
-	writeTSCReg( 0x12,0x81);
-	writeTSCReg( 0x13,0x82);
-	writeTSCReg( 0x51,0x82);
-	writeTSCReg( 0x51,0x00);
-	writeTSCReg( 0x04,0x03);
-	writeTSCReg( 0x05,0xA1);
-	writeTSCReg( 0x06,0x15);
-	writeTSCReg( 0x0B,0x87);
-	writeTSCReg( 0x0C,0x83);
-	writeTSCReg( 0x12,0x87);
-	writeTSCReg( 0x13,0x83);
-	writeTSCReg(0,3);
-	readTSCReg(0x10);
-	writeTSCReg(0x10,0x08);
-	writeTSCReg(0,4);
-	writeTSCReg(0x08,0x7F);
-	writeTSCReg(0x09,0xE1);
-	writeTSCReg(0xa,0x80);
-	writeTSCReg(0xb,0x1F);
-	writeTSCReg(0xc,0x7F);
-	writeTSCReg(0xd,0xC1);
-	writeTSCReg(0,0);
-	writeTSCReg( 0x41, 0x08);
-	writeTSCReg( 0x42, 0x08);
-	writeTSCReg( 0x3A, 0x00);
-	writeTSCReg(0,4);
-	writeTSCReg(0x08,0x7F);
-	writeTSCReg(0x09,0xE1);
-	writeTSCReg(0xa,0x80);
-	writeTSCReg(0xb,0x1F);
-	writeTSCReg(0xc,0x7F);
-	writeTSCReg(0xd,0xC1);
-	writeTSCReg(0,1);
-	writeTSCReg(0x2F, 0x2B);
-	writeTSCReg(0x30, 0x40);
-	writeTSCReg(0x31, 0x40);
-	writeTSCReg(0x32, 0x60);
-	writeTSCReg(0,0);
-	readTSCReg( 0x74);
-	writeTSCReg( 0x74, 0x02);
-	readTSCReg( 0x74);
-	writeTSCReg( 0x74, 0x10);
-	readTSCReg( 0x74);
-	writeTSCReg( 0x74, 0x40);
-	writeTSCReg(0,1);
-	writeTSCReg( 0x21, 0x20);
-	writeTSCReg( 0x22, 0xF0);
-	writeTSCReg(0,0);
-	readTSCReg( 0x51);
-	readTSCReg( 0x3f);
-	writeTSCReg( 0x3f, 0xd4);
-	writeTSCReg(0,1);
-	writeTSCReg(0x23,0x44);
-	writeTSCReg(0x1F,0xD4);
-	writeTSCReg(0x28,0x4e);
-	writeTSCReg(0x29,0x4e);
-	writeTSCReg(0x24,0x9e);
-	writeTSCReg(0x24,0x9e);
-	writeTSCReg(0x20,0xD4);
-	writeTSCReg(0x2a,0x14);
-	writeTSCReg(0x2b,0x14);
-	writeTSCReg(0x26,volLevel);
-	writeTSCReg(0x27,volLevel);
-	writeTSCReg(0,0);
-	writeTSCReg(0x40,0);
-	writeTSCReg(0x3a,0x60);
-	writeTSCReg(0,1);
-	writeTSCReg(0x26,volLevel);
-	writeTSCReg(0x27,volLevel);
-	writeTSCReg(0x2e,0x03);
-	writeTSCReg(0,3);
-	writeTSCReg(3,0);
-	writeTSCReg(0,1);
-	writeTSCReg(0x21,0x20);
-	writeTSCReg(0x22,0xF0);
-	readTSCReg(0x22);
-	writeTSCReg(0x22,0xF0);
-	writeTSCReg(0,0);
-	writeTSCReg(0x52,0x80);
-	writeTSCReg(0x51,0x00);
-	writeTSCReg(0,3);
-	readTSCReg(0x02);
-	writeTSCReg(2,0x98);
-	writeTSCReg(0,0xff);
-	writeTSCReg(5,0);
-
-	writePowerManagement(0x00,0x0D);
-}
-
 void fifocheck (void)
 {
-
 	if(*((vu32*)0x027FFE24) == (u32)0x027FFE04)
 	{
-		if(fifoCheckValue32(FIFO_USER_08)) { NDSTouchscreenMode(); }
+		REG_SCFG_ROM = 0x703;
-		if(fifoCheckValue32(FIFO_USER_04)) {
+
-			if(fifoCheckValue32(FIFO_USER_05)) { REG_SCFG_CLK = 0x0181; } else { REG_SCFG_CLK = 0x0180; }
+		if(fifoCheckValue32(FIFO_USER_05)) { REG_SCFG_CLK = 0x0180; } else { REG_SCFG_CLK = 0x0187; }
-		}
+		
-		if(fifoCheckValue32(FIFO_USER_06)) { /*Do Nothing*/ } else { REG_SCFG_ROM = 0x703; }
+		REG_MBK6=0x09403900;
-		if(fifoCheckValue32(FIFO_USER_05)) { REG_SCFG_EXT = 0x93A53000; } else { REG_SCFG_EXT = 0x12A03000; }
+		REG_MBK7=0x09803940;
+		REG_MBK8=0x09C03980;
+		REG_MBK9=0xFCFFFF0F;
+
+		REG_SCFG_EXT = 0x12A03000;
+
 		irqDisable (IRQ_ALL);
 		*((vu32*)0x027FFE34) = (u32)0x06000000;
 

arm7/source/main.c

@@ -50,9 +50,12 @@ int main(void) {
 
 	irqEnable( IRQ_VBLANK | IRQ_VCOUNT );
 	
+	i2cWriteRegister(0x4A, 0x12, 0x00);	// Press power-button for auto-reset
+	i2cWriteRegister(0x4A, 0x70, 0x01);	// Bootflag = Warmboot/SkipHealthSafety
+
 	fifoWaitValue32(FIFO_USER_01);
 	if(fifoCheckValue32(FIFO_USER_02)) { 
-		if(fifoCheckValue32(FIFO_USER_07)) { TWL_ResetSlot1(); } else { PowerOnSlot(); }
+		if(fifoCheckValue32(FIFO_USER_04)) { TWL_ResetSlot1(); } else { PowerOnSlot(); }
 	}
 	fifoSendValue32(FIFO_USER_03, 1);
 		

arm9/source/launch_engine.c

@@ -35,7 +35,8 @@ void vramcpy (void* dst, const void* src, int len)
 }	
 
 // Basic engine with no cheat related code.
-void runLaunchEngine (bool TWLCLOCK, bool EnableSD)
+// void runLaunchEngine (bool TWLCLOCK, bool EnableSD)
+void runLaunchEngine(bool TWLCLOCK)
 {
 
 	irqDisable(IRQ_ALL);
@@ -52,22 +53,21 @@ void runLaunchEngine (bool TWLCLOCK, bool EnableSD)
 	// Give the VRAM to the ARM7
 	VRAM_C_CR = VRAM_ENABLE | VRAM_C_ARM7_0x06000000;
 	
-	if( TWLCLOCK ) {
-		if( EnableSD ) {
-			REG_SCFG_EXT=0x83002000;
-		} else {
-			REG_SCFG_EXT=0x03002000;
-		}
-	} else {
-		if( EnableSD ) {
-			REG_SCFG_EXT=0x83000000;
-		} else {
-			REG_SCFG_EXT=0x03000000;
-		}
-	}
-	
 	// Reset into a passme loop
 	REG_EXMEMCNT |= ARM7_OWNS_ROM | ARM7_OWNS_CARD;
+
+	*((vu32*)REG_MBK1)=0x8D898581;
+	*((vu32*)REG_MBK2)=0x91898581;
+	*((vu32*)REG_MBK3)=0x91999591;
+	*((vu32*)REG_MBK4)=0x91898581;
+	*((vu32*)REG_MBK5)=0x91999591;
+
+	REG_MBK6=0x00003000;
+	REG_MBK7=0x00003000;
+	REG_MBK8=0x00003000;
+
+	if( TWLCLOCK ) { REG_SCFG_EXT=0x03002000; } else { REG_SCFG_EXT=0x03000000; }
+
 	*((vu32*)0x027FFFFC) = 0;
 	*((vu32*)0x027FFE04) = (u32)0xE59FF018;
 	*((vu32*)0x027FFE24) = (u32)0x027FFE04;

arm9/source/launch_engine.h

@@ -25,7 +25,7 @@
 extern "C" {
 #endif
 
-void runLaunchEngine (bool TWLCLOCK, bool EnableSD);
+void runLaunchEngine(bool TWLCLOCK);
 
 #ifdef __cplusplus
 }

arm9/source/main.cpp

@@ -40,11 +40,10 @@
 
 int main() {
 
-	defaultExceptionHandler();
+	// defaultExceptionHandler();
-
+	
 	bool TWLCLOCK = false;
-	bool EnableSD = false;
+	
-
 	// If slot is powered off, tell Arm7 slot power on is required.
 	if(REG_SCFG_MC == 0x11) { fifoSendValue32(FIFO_USER_02, 1); }
 	if(REG_SCFG_MC == 0x10) { fifoSendValue32(FIFO_USER_02, 1); }
@@ -55,37 +54,22 @@ int main() {
 	BootSplashInit();
 
 	if (fatInitDefault()) {
-		CIniFile ntrlauncher_config( "sd:/nds/ntr_launcher.ini" );
+		CIniFile ntrlauncher_config( "sd:/nds/NTR_Launcher.ini" );
 		
-		if(ntrlauncher_config.GetInt("NTRLAUNCHER","TWLCLOCK",0) == 0) { /* */ } else {  TWLCLOCK = true; }
-		
-		if( TWLCLOCK == false ) {
-			fifoSendValue32(FIFO_USER_04, 1);
-			REG_SCFG_CLK = 0x80;
-			swiWaitForVBlank();
-		}
-
-		if(ntrlauncher_config.GetInt("NTRLAUNCHER","ENABLESD",0) == 0) { /* */ } else {
-			EnableSD = true;
-			// Tell Arm7 to use alternate SCFG_EXT values.
-			fifoSendValue32(FIFO_USER_05, 1);
-		}
-
-		if(ntrlauncher_config.GetInt("NTRLAUNCHER","TWLMODE",0) == 0) {
-			if(ntrlauncher_config.GetInt("NTRLAUNCHER","NTRTOUCH",0) == 0) { /* Nothing */ } else { fifoSendValue32(FIFO_USER_08, 1); }
-		} else {
-			// Tell Arm7 not to switch into NTR mode (this will only work on alt build of NTR Launcher)
-			fifoSendValue32(FIFO_USER_06, 1);
-		}
-
 		if(ntrlauncher_config.GetInt("NTRLAUNCHER","RESETSLOT1",0) == 0) { /* */ } else {
 			fifoSendValue32(FIFO_USER_02, 1);
-			fifoSendValue32(FIFO_USER_07, 1);
+			fifoSendValue32(FIFO_USER_04, 1);
 		}
+
+		if(ntrlauncher_config.GetInt("NTRLAUNCHER","TWLCLOCK",0) == 0) {
+			fifoSendValue32(FIFO_USER_05, 1);
+			REG_SCFG_CLK = 0x80;
+			swiWaitForVBlank();
+		} else { REG_SCFG_CLK = 0x85; TWLCLOCK = true; }
 		
 	} else {
 		fifoSendValue32(FIFO_USER_02, 1);
-		fifoSendValue32(FIFO_USER_07, 1);
+		fifoSendValue32(FIFO_USER_04, 1);
 	}
 
 	// Tell Arm7 it's ready for card reset (if card reset is nessecery)
@@ -93,14 +77,13 @@ int main() {
 	// Waits for Arm7 to finish card reset (if nessecery)
 	fifoWaitValue32(FIFO_USER_03);
 
-	// Wait for card to stablize before continuing
+	for (int i = 0; i < 40; i++) { swiWaitForVBlank(); }
-	for (int i = 0; i < 30; i++) { swiWaitForVBlank(); }
 	
 	sysSetCardOwner (BUS_OWNER_ARM9);
 
 	getHeader (ndsHeader);
 	
-	for (int i = 0; i < 30; i++) { swiWaitForVBlank(); }
+	for (int i = 0; i < 40; i++) { swiWaitForVBlank(); }
 	
 	memcpy (gameid, ((const char*)ndsHeader) + 12, 4);
 
@@ -110,7 +93,7 @@ int main() {
 			for (int i = 0; i < 300; i++) { swiWaitForVBlank(); }
 			break;
 		} else {
-			runLaunchEngine (TWLCLOCK, EnableSD);
+			runLaunchEngine(TWLCLOCK);
 		}
 	}
 	return 0;